High-speed redundant modulo 2n-1 adder

F. Kharbash, G. M. Chaudhry

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Modular adders are widely used in Residue Number System arithmetic. Their performance is restricted due to the hardware implementation complexity. In this work, we investigate the design of a redundant modulo number system and present hardware architecture for performing the redundant modulo 2n-1 addition with a constant time feature using the Binary Signed Digit Number (BSDN) System. We developed a set of logical equations that describe the BSDN full adder operation and later used it as a building block to construct the redundant modulo 2n-1 adder. The proposed architecture has a constant delay equals to the delay of one BSDN FA and an area equals to n * (BSDN FA area), where n is the word length. We also presented a strategy to improve the design by considering the different combinations of the operands.

Original languageEnglish
Title of host publicationIEEE International Conference on Computer Systems and Applications, 2006
PublisherIEEE Computer Society
Pages80-87
Number of pages8
ISBN (Print)1424402123, 9781424402120
DOIs
Publication statusPublished - 2006
Externally publishedYes
EventIEEE International Conference on Computer Systems and Applications, 2006 - Sharjah, United Arab Emirates
Duration: Mar 8 2006Mar 8 2006

Publication series

NameIEEE International Conference on Computer Systems and Applications, 2006
Volume2006

Other

OtherIEEE International Conference on Computer Systems and Applications, 2006
Country/TerritoryUnited Arab Emirates
CitySharjah
Period3/8/063/8/06

ASJC Scopus subject areas

  • Engineering(all)

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