High-speed redundant modulo 2ⁿ-1 adder

Modular adders are widely used in Residue Number System arithmetic. Their performance is restricted due to the hardware implementation complexity. In this work, we investigate the design of a redundant modulo number system and present hardware architecture for performing the redundant modulo 2ⁿ-1 addition with a constant time feature using the Binary Signed Digit Number (BSDN) System. We developed a set of logical equations that describe the BSDN full adder operation and later used it as a building block to construct the redundant modulo 2ⁿ-1 adder. The proposed architecture has a constant delay equals to the delay of one BSDN FA and an area equals to n * (BSDN FA area), where n is the word length. We also presented a strategy to improve the design by considering the different combinations of the operands.