TY - GEN
T1 - High-speed redundant modulo 2n-1 adder
AU - Kharbash, F.
AU - Chaudhry, G. M.
PY - 2006
Y1 - 2006
N2 - Modular adders are widely used in Residue Number System arithmetic. Their performance is restricted due to the hardware implementation complexity. In this work, we investigate the design of a redundant modulo number system and present hardware architecture for performing the redundant modulo 2n-1 addition with a constant time feature using the Binary Signed Digit Number (BSDN) System. We developed a set of logical equations that describe the BSDN full adder operation and later used it as a building block to construct the redundant modulo 2n-1 adder. The proposed architecture has a constant delay equals to the delay of one BSDN FA and an area equals to n * (BSDN FA area), where n is the word length. We also presented a strategy to improve the design by considering the different combinations of the operands.
AB - Modular adders are widely used in Residue Number System arithmetic. Their performance is restricted due to the hardware implementation complexity. In this work, we investigate the design of a redundant modulo number system and present hardware architecture for performing the redundant modulo 2n-1 addition with a constant time feature using the Binary Signed Digit Number (BSDN) System. We developed a set of logical equations that describe the BSDN full adder operation and later used it as a building block to construct the redundant modulo 2n-1 adder. The proposed architecture has a constant delay equals to the delay of one BSDN FA and an area equals to n * (BSDN FA area), where n is the word length. We also presented a strategy to improve the design by considering the different combinations of the operands.
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U2 - 10.1109/aiccsa.2006.205071
DO - 10.1109/aiccsa.2006.205071
M3 - Conference contribution
AN - SCOPUS:33750845303
SN - 1424402123
SN - 9781424402120
T3 - IEEE International Conference on Computer Systems and Applications, 2006
SP - 80
EP - 87
BT - IEEE International Conference on Computer Systems and Applications, 2006
PB - IEEE Computer Society
T2 - IEEE International Conference on Computer Systems and Applications, 2006
Y2 - 8 March 2006 through 8 March 2006
ER -