TY - GEN
T1 - Highly reliable and low-power full adder cell
AU - Ibrahim, Walid
AU - Beg, Azam
AU - Beiu, Valeriu
PY - 2011
Y1 - 2011
N2 - Full adders (FAs) are essential for digital circuits including microprocessors, digital signal processors, and microcontrollers. Both the power consumption and the reliability of FAs are crucial as they directly affect: arithmetic logic units, floating-point units, as well as memory address calculations. This paper studies the effect threshold voltage (V TH) variations play on the reliability of a classical 28-transistor FA, and shows that reliability can be enhanced without increasing the occupied area, and while also reducing power consumption. An enabling transistor sizing scheme is used to improve on reliability without increasing power consumption (as reducing and limiting currents). The proposed FA in 16nm predictive technology model (PTM) is significantly more reliable (six orders of magnitude in case of Cout, and three orders of magnitude in case of Sum at 10% input variations) and dissipates 38× less than a classical FA, while being 6× slower.
AB - Full adders (FAs) are essential for digital circuits including microprocessors, digital signal processors, and microcontrollers. Both the power consumption and the reliability of FAs are crucial as they directly affect: arithmetic logic units, floating-point units, as well as memory address calculations. This paper studies the effect threshold voltage (V TH) variations play on the reliability of a classical 28-transistor FA, and shows that reliability can be enhanced without increasing the occupied area, and while also reducing power consumption. An enabling transistor sizing scheme is used to improve on reliability without increasing power consumption (as reducing and limiting currents). The proposed FA in 16nm predictive technology model (PTM) is significantly more reliable (six orders of magnitude in case of Cout, and three orders of magnitude in case of Sum at 10% input variations) and dissipates 38× less than a classical FA, while being 6× slower.
KW - CMOS
KW - Full adder
KW - energy
KW - power
KW - reliability
UR - http://www.scopus.com/inward/record.url?scp=84858974126&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84858974126&partnerID=8YFLogxK
U2 - 10.1109/NANO.2011.6144434
DO - 10.1109/NANO.2011.6144434
M3 - Conference contribution
AN - SCOPUS:84858974126
SN - 9781457715143
T3 - Proceedings of the IEEE Conference on Nanotechnology
SP - 500
EP - 503
BT - 2011 11th IEEE International Conference on Nanotechnology, NANO 2011
T2 - 2011 11th IEEE International Conference on Nanotechnology, NANO 2011
Y2 - 15 August 2011 through 19 August 2011
ER -