Identifying the Worst Reliability Input Vectors and the Associated Critical Logic Gates

Research output: Contribution to journalArticlepeer-review

14 Citations (Scopus)


Scaling the CMOS devices deep into the nanorange reduces their reliability margins significantly. Consequently, accurately calculating the reliability of digital nanocircuits is becoming a necessity for investigating design alternatives to optimize the trade-offs between area-power-delay and reliability. However, accurate reliability calculation of large and highly connected circuits is complex and very time consuming. This paper proposes a progressive consensus-based algorithm for identifying the worst reliability input vectors and the associated critical logic gates. Improving the reliability of the critical gates helps circuit designers to effectively improve the circuit overall reliability while having a minimal impact on the traditional power-area-deal design parameters. The accuracy and efficiency of the algorithm can be tuned to fit a variety of applications. The algorithm scales well with circuit size, and is independent of the interconnect complexity and the logic depth. Extensive computational results show that the accuracy and the efficiency of the proposed algorithm are better than the most recent results reported in the literature.

Original languageEnglish
Article number7163530
Pages (from-to)1748-1760
Number of pages13
JournalIEEE Transactions on Computers
Issue number6
Publication statusPublished - Jun 1 2016


  • Reliability
  • genetic algorithms
  • heuristics algorithms
  • logic circuits
  • optimization
  • simulated annealing
  • worst-case analysis

ASJC Scopus subject areas

  • Software
  • Theoretical Computer Science
  • Hardware and Architecture
  • Computational Theory and Mathematics


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