TY - GEN
T1 - Implementation of PRINCE algorithm in FPGA
AU - Abbas, Yasir Amer
AU - Jidin, Razali
AU - Jamil, Norziana
AU - Z'aba, Muhammad Reza
AU - Rusli, Mohd Ezanee
AU - Tariq, Baraa
N1 - Publisher Copyright:
© 2014 IEEE.
PY - 2014
Y1 - 2014
N2 - This paper presents a hardware implementation of the PRINCE block cipher in Field Programmable Gate Array (FPGA). In many security applications, the software implementations of cryptographic algorithms are slow and inefficient. In order to solve the problems, a new FPGA architecture was proposed to speed up the performance and flexibility of PRINCE algorithm. The concurrent computing design allows an encryption block data of 64 bits within one clock cycle, reducing the hardware area and producing a high throughput and low latency. It also showed high speed processing and consumed low power. To do this, firstly, the encryption, decryption and key schedule are all implemented with small hardware resources, Next, an efficient hardware architectural model for PRINCE algorithms was developed using very high speed integrated circuit hardware description language (VHDL). Finally, the VHDL design for PRINCE algorithm was synthesized in FPGA boards. Two FPGA boards were used in this study, which are Virtex-4 and Virtex-6. The results show a throughput of 2.03 Gbps and efficiency of 2.126 Mbps/slice for Virtex-4, whereas a throughput of 4.18 Gbps and efficiency of 8.681 Mbps/slice for Virtex-6.
AB - This paper presents a hardware implementation of the PRINCE block cipher in Field Programmable Gate Array (FPGA). In many security applications, the software implementations of cryptographic algorithms are slow and inefficient. In order to solve the problems, a new FPGA architecture was proposed to speed up the performance and flexibility of PRINCE algorithm. The concurrent computing design allows an encryption block data of 64 bits within one clock cycle, reducing the hardware area and producing a high throughput and low latency. It also showed high speed processing and consumed low power. To do this, firstly, the encryption, decryption and key schedule are all implemented with small hardware resources, Next, an efficient hardware architectural model for PRINCE algorithms was developed using very high speed integrated circuit hardware description language (VHDL). Finally, the VHDL design for PRINCE algorithm was synthesized in FPGA boards. Two FPGA boards were used in this study, which are Virtex-4 and Virtex-6. The results show a throughput of 2.03 Gbps and efficiency of 2.126 Mbps/slice for Virtex-4, whereas a throughput of 4.18 Gbps and efficiency of 8.681 Mbps/slice for Virtex-6.
KW - Block cipher
KW - FPGA
KW - PRINCE
KW - VHDL
UR - http://www.scopus.com/inward/record.url?scp=84937405931&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84937405931&partnerID=8YFLogxK
U2 - 10.1109/ICIMU.2014.7066593
DO - 10.1109/ICIMU.2014.7066593
M3 - Conference contribution
AN - SCOPUS:84937405931
T3 - Conference Proceedings - 6th International Conference on Information Technology and Multimedia at UNITEN: Cultivating Creativity and Enabling Technology Through the Internet of Things, ICIMU 2014
SP - 1
EP - 4
BT - Conference Proceedings - 6th International Conference on Information Technology and Multimedia at UNITEN
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 6th International Conference on Information Technology and Multimedia, ICIMU 2014
Y2 - 18 November 2014 through 20 November 2014
ER -