TY - GEN
T1 - Improved instruction fetching with a new block-based cache scheme
AU - Beg, Azam
AU - Chu, Yul
PY - 2005
Y1 - 2005
N2 - Instruction fetch speeds are Improved by using cache schemes that are based on dynamic (low of program instructions. Variable-Sized Black Cache (VSBC) is a new instruction scheme that stores basic code blocks and their boundaries as traces. Current trace- or block-based cache schemes usually have some instructions stored repeatedly; this redundancy is eliminated in VSBC. The studies done so far, in single- and multi-threaded environments, have shown improvements in trace miss rate. Other aspects of VSBC performance such as trace length and latency are being studied.
AB - Instruction fetch speeds are Improved by using cache schemes that are based on dynamic (low of program instructions. Variable-Sized Black Cache (VSBC) is a new instruction scheme that stores basic code blocks and their boundaries as traces. Current trace- or block-based cache schemes usually have some instructions stored repeatedly; this redundancy is eliminated in VSBC. The studies done so far, in single- and multi-threaded environments, have shown improvements in trace miss rate. Other aspects of VSBC performance such as trace length and latency are being studied.
UR - http://www.scopus.com/inward/record.url?scp=33749064336&partnerID=8YFLogxK
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U2 - 10.1109/ISSCS.2005.1511353
DO - 10.1109/ISSCS.2005.1511353
M3 - Conference contribution
AN - SCOPUS:33749064336
SN - 0780390296
SN - 9780780390294
T3 - ISSCS 2005: International Symposium on Signals, Circuits and Systems - Proceedings
SP - 765
EP - 768
BT - ISSCS 2005
T2 - ISSCS 2005: International Symposium on Signals, Circuits and Systems
Y2 - 14 July 2005 through 15 July 2005
ER -