Learning from Examples and VLSI Implementation of Neural Networks

Valeriu Beiu; Jan A. Peperstraete; Joos Vandewalle; Rudy Lauwereins

Learning from Examples and VLSI Implementation of Neural Networks

Valeriu Beiu, Jan A. Peperstraete, Joos Vandewalle, Rudy Lauwereins

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

The paper details a direct design alternative to the learning techniques used for determining the synaptic weights of a neural network, optimizing the area of its VLSI implementation. We consider binary neurons having a threshold nonlinear transfer function. The problem to be solved is to find a network when m examples of n input bits are given. The optimum criterion is changed from size-and-depth of the network, to the classical AT 2 complexity measure of VLSI circuits (A is the area of the chip, and T is the time for propagating the inputs to the outputs). Considering the maximum fan-in of one neuron as a parameter we proceed to show its influence on the area, and suggest how to obtain a full class of solutions. Results are promising, and further directions for research are pointed out in the conclusions, together with some open questions.

Original language	English
Title of host publication	European Meeting on Cybernetics and System Research
Publication status	Published - Apr 5 1994
Event	EMCSR'94 - Vienna, Austria Duration: Apr 5 1994 → …

Conference

Conference	EMCSR'94
Period	4/5/94 → …

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@inproceedings{b861626ee78e4042843c722d30a8a906,

title = "Learning from Examples and VLSI Implementation of Neural Networks",

abstract = "The paper details a direct design alternative to the learning techniques used for determining the synaptic weights of a neural network, optimizing the area of its VLSI implementation. We consider binary neurons having a threshold nonlinear transfer function. The problem to be solved is to find a network when m examples of n input bits are given. The optimum criterion is changed from size-and-depth of the network, to the classical AT 2 complexity measure of VLSI circuits (A is the area of the chip, and T is the time for propagating the inputs to the outputs). Considering the maximum fan-in of one neuron as a parameter we proceed to show its influence on the area, and suggest how to obtain a full class of solutions. Results are promising, and further directions for research are pointed out in the conclusions, together with some open questions.",

author = "Valeriu Beiu and Peperstraete, {Jan A.} and Joos Vandewalle and Rudy Lauwereins",

year = "1994",

month = apr,

day = "5",

language = "English",

booktitle = "European Meeting on Cybernetics and System Research",

note = "EMCSR'94 ; Conference date: 05-04-1994",

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TY - GEN

T1 - Learning from Examples and VLSI Implementation of Neural Networks

AU - Beiu, Valeriu

AU - Peperstraete, Jan A.

AU - Vandewalle, Joos

AU - Lauwereins, Rudy

PY - 1994/4/5

Y1 - 1994/4/5

N2 - The paper details a direct design alternative to the learning techniques used for determining the synaptic weights of a neural network, optimizing the area of its VLSI implementation. We consider binary neurons having a threshold nonlinear transfer function. The problem to be solved is to find a network when m examples of n input bits are given. The optimum criterion is changed from size-and-depth of the network, to the classical AT 2 complexity measure of VLSI circuits (A is the area of the chip, and T is the time for propagating the inputs to the outputs). Considering the maximum fan-in of one neuron as a parameter we proceed to show its influence on the area, and suggest how to obtain a full class of solutions. Results are promising, and further directions for research are pointed out in the conclusions, together with some open questions.

AB - The paper details a direct design alternative to the learning techniques used for determining the synaptic weights of a neural network, optimizing the area of its VLSI implementation. We consider binary neurons having a threshold nonlinear transfer function. The problem to be solved is to find a network when m examples of n input bits are given. The optimum criterion is changed from size-and-depth of the network, to the classical AT 2 complexity measure of VLSI circuits (A is the area of the chip, and T is the time for propagating the inputs to the outputs). Considering the maximum fan-in of one neuron as a parameter we proceed to show its influence on the area, and suggest how to obtain a full class of solutions. Results are promising, and further directions for research are pointed out in the conclusions, together with some open questions.

M3 - Conference contribution

BT - European Meeting on Cybernetics and System Research

T2 - EMCSR'94

Y2 - 5 April 1994

ER -

Learning from Examples and VLSI Implementation of Neural Networks

Abstract

Conference

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