TY - GEN
T1 - LNA design for on-chip RF test
AU - Ramzan, Rashad
AU - Lei, Zou
AU - Da̧browski, Jerzy
PY - 2006
Y1 - 2006
N2 - In this paper we present two CMOS LNA blocks designed for integration with other RF frontend blocks for onchip test. Both of them are variants of the source degenerated LNA with embedded switches and/or a multiplexer, optimized with respect to their function and location. We discuss their functionality and performances in terms of test mode and the normal operation mode. The circuits are designed for 0.35μm CMOS process. Simulation results obtained at 2.4 GHz frequency, show a tradeoff between performance and testability. Nevertheless, the LNA circuit, which only uses embedded switches, proves a satisfactory design.
AB - In this paper we present two CMOS LNA blocks designed for integration with other RF frontend blocks for onchip test. Both of them are variants of the source degenerated LNA with embedded switches and/or a multiplexer, optimized with respect to their function and location. We discuss their functionality and performances in terms of test mode and the normal operation mode. The circuits are designed for 0.35μm CMOS process. Simulation results obtained at 2.4 GHz frequency, show a tradeoff between performance and testability. Nevertheless, the LNA circuit, which only uses embedded switches, proves a satisfactory design.
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M3 - Conference contribution
AN - SCOPUS:34547371564
SN - 0780393902
SN - 9780780393905
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 4236
EP - 4239
BT - ISCAS 2006
T2 - ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems
Y2 - 21 May 2006 through 24 May 2006
ER -