Low Activity-Factor Test Pattern Generation

Azam Beg, Manzoor Khan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)


As the complexity and the sizes of modern digital circuits have increased, so has the cost of testing them. Decreasing the test time to a minimum while keeping high test coverage is highly desirable. Completely random or pseudo-random test patterns can result in high switching activity and hence high test equipment power consumption. This work proposes using genetic algorithms (GAs) to automatically generate the test patterns that have low switching activity on the circuit inputs and hence reduced switching power dissipation. At this stage, the usefulness of the proposed method has been demonstrated using combinational circuits of medium complexity. For small circuits, the reduction in activity factor (AF) ranges between 14% and 38%, whereas larger circuits show the AF drops between 85% and 97%. Additionally, the proposed method decreases the number of test patterns while maintaining high test coverage.

Original languageEnglish
Title of host publicationProceedings - 2020 IEEE International Conference on Semiconductor Electronics, ICSE 2020
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages4
ISBN (Electronic)9781728159676
Publication statusPublished - Jul 2020
Event14th IEEE International Conference on Semiconductor Electronics, ICSE 2020 - Kuala Lumpur, Malaysia
Duration: Jul 28 2020Jul 29 2020

Publication series

NameIEEE International Conference on Semiconductor Electronics, Proceedings, ICSE


Conference14th IEEE International Conference on Semiconductor Electronics, ICSE 2020
CityKuala Lumpur


  • Combinational circuit
  • activity factor
  • fault detection
  • genetic algorithms
  • power consumption
  • test pattern

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials


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