Low Activity-Factor Test Pattern Generation

As the complexity and the sizes of modern digital circuits have increased, so has the cost of testing them. Decreasing the test time to a minimum while keeping high test coverage is highly desirable. Completely random or pseudo-random test patterns can result in high switching activity and hence high test equipment power consumption. This work proposes using genetic algorithms (GAs) to automatically generate the test patterns that have low switching activity on the circuit inputs and hence reduced switching power dissipation. At this stage, the usefulness of the proposed method has been demonstrated using combinational circuits of medium complexity. For small circuits, the reduction in activity factor (AF) ranges between 14% and 38%, whereas larger circuits show the AF drops between 85% and 97%. Additionally, the proposed method decreases the number of test patterns while maintaining high test coverage.