Low power and highly reliable gates using arrays of optimally sized transistors

V. Beiu; L. Iordǎconiu; A. Beg; W. Ibrahim; F. Kharbash

doi:10.1109/SMICND.2012.6400738

Low power and highly reliable gates using arrays of optimally sized transistors

V. Beiu, L. Iordǎconiu, A. Beg, W. Ibrahim, F. Kharbash

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

This paper introduces an enabling transistor sizing method for classical CMOS gates in advanced technology nodes through simple examples. The well-known CMOS inverter is used here both for presenting the different sizing options as well as for simulations for weighting performances. These preliminary results show that sizing is far from exhausting its potential as still allowing to: (i) improve delay and power; (ii) increase the static noise margins (SNMs); (iii) modify threshold voltages (V_TH); and also (iv) reduce V_TH variations (σ_VTH).

Original language	English
Title of host publication	2012 International Semiconductor Conference, CAS 2012 Proceedings
Pages	433-436
Number of pages	4
DOIs	https://doi.org/10.1109/SMICND.2012.6400738
Publication status	Published - 2012
Event	35th International Semiconductor Conference, CAS 2012 - Sinaia, Romania Duration: Oct 15 2012 → Oct 17 2012

Publication series

Name	Proceedings of the International Semiconductor Conference, CAS
Volume	2

Conference

Conference	35th International Semiconductor Conference, CAS 2012
Country/Territory	Romania
City	Sinaia
Period	10/15/12 → 10/17/12

Keywords

CMOS
arrays
inverter
power
sizing

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering

Access to Document

10.1109/SMICND.2012.6400738

Cite this

Beiu, V., Iordǎconiu, L., Beg, A., Ibrahim, W., & Kharbash, F. (2012). Low power and highly reliable gates using arrays of optimally sized transistors. In 2012 International Semiconductor Conference, CAS 2012 Proceedings (pp. 433-436). Article 6400738 (Proceedings of the International Semiconductor Conference, CAS; Vol. 2). https://doi.org/10.1109/SMICND.2012.6400738

Low power and highly reliable gates using arrays of optimally sized transistors. / Beiu, V.; Iordǎconiu, L.; Beg, A. et al.
2012 International Semiconductor Conference, CAS 2012 Proceedings. 2012. p. 433-436 6400738 (Proceedings of the International Semiconductor Conference, CAS; Vol. 2).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Beiu, V, Iordǎconiu, L, Beg, A , Ibrahim, W & Kharbash, F 2012, Low power and highly reliable gates using arrays of optimally sized transistors. in 2012 International Semiconductor Conference, CAS 2012 Proceedings., 6400738, Proceedings of the International Semiconductor Conference, CAS, vol. 2, pp. 433-436, 35th International Semiconductor Conference, CAS 2012, Sinaia, Romania, 10/15/12. https://doi.org/10.1109/SMICND.2012.6400738

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AB - This paper introduces an enabling transistor sizing method for classical CMOS gates in advanced technology nodes through simple examples. The well-known CMOS inverter is used here both for presenting the different sizing options as well as for simulations for weighting performances. These preliminary results show that sizing is far from exhausting its potential as still allowing to: (i) improve delay and power; (ii) increase the static noise margins (SNMs); (iii) modify threshold voltages (VTH); and also (iv) reduce VTH variations (σVTH).

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Low power and highly reliable gates using arrays of optimally sized transistors

Abstract

Publication series

Conference

Keywords

ASJC Scopus subject areas

Access to Document

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Cite this