Power dissipation and reliability are two major challenges when designing gates and circuits using nanoscale devices. This paper proposes a novel approach for the design of CMOS logic gates which aims to simultaneously decrease their power consumption and their probabilities of failure. This new sizing method was evaluated on CMOS inverters and NOR-2 gates at three technology nodes: 16nm, 22nm, and 32nm. The new inverters and NOR-2 were compared to the classic gates. The results show that the new gates have significantly lower power and higher reliability when compared to classic CMOS gates. The results also suggest that the advantages of the new design method are enhanced at smaller feature sizes: at 16nm the new gates outperform the classic ones in reliability, power, and PDP.