Low-power and highly reliable logic gates transistor-level optimizations

Mawahib Hussein Sulieman; Valeriu Beiu; Walid Ibrahim

doi:10.1109/NANO.2010.5697892

Low-power and highly reliable logic gates transistor-level optimizations

Mawahib Hussein Sulieman, Valeriu Beiu, Walid Ibrahim

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

20 Citations (Scopus)

Abstract

Power dissipation and reliability are two major challenges when designing gates and circuits using nanoscale devices. This paper proposes a novel approach for the design of CMOS logic gates which aims to simultaneously decrease their power consumption and their probabilities of failure. This new sizing method was evaluated on CMOS inverters and NOR-2 gates at three technology nodes: 16nm, 22nm, and 32nm. The new inverters and NOR-2 were compared to the classic gates. The results show that the new gates have significantly lower power and higher reliability when compared to classic CMOS gates. The results also suggest that the advantages of the new design method are enhanced at smaller feature sizes: at 16nm the new gates outperform the classic ones in reliability, power, and PDP.

Original language	English
Title of host publication	2010 10th IEEE Conference on Nanotechnology, NANO 2010
Pages	254-257
Number of pages	4
DOIs	https://doi.org/10.1109/NANO.2010.5697892
Publication status	Published - 2010
Event	2010 10th IEEE Conference on Nanotechnology, NANO 2010 - Ilsan, Gyeonggi-Do, Korea, Republic of Duration: Aug 17 2010 → Aug 20 2010

Publication series

Name	2010 10th IEEE Conference on Nanotechnology, NANO 2010

Other

Other	2010 10th IEEE Conference on Nanotechnology, NANO 2010
Country/Territory	Korea, Republic of
City	Ilsan, Gyeonggi-Do
Period	8/17/10 → 8/20/10

ASJC Scopus subject areas

Atomic and Molecular Physics, and Optics

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10.1109/NANO.2010.5697892

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Sulieman, MH, Beiu, V & Ibrahim, W 2010, Low-power and highly reliable logic gates transistor-level optimizations. in 2010 10th IEEE Conference on Nanotechnology, NANO 2010., 5697892, 2010 10th IEEE Conference on Nanotechnology, NANO 2010, pp. 254-257, 2010 10th IEEE Conference on Nanotechnology, NANO 2010, Ilsan, Gyeonggi-Do, Korea, Republic of, 8/17/10. https://doi.org/10.1109/NANO.2010.5697892

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AB - Power dissipation and reliability are two major challenges when designing gates and circuits using nanoscale devices. This paper proposes a novel approach for the design of CMOS logic gates which aims to simultaneously decrease their power consumption and their probabilities of failure. This new sizing method was evaluated on CMOS inverters and NOR-2 gates at three technology nodes: 16nm, 22nm, and 32nm. The new inverters and NOR-2 were compared to the classic gates. The results show that the new gates have significantly lower power and higher reliability when compared to classic CMOS gates. The results also suggest that the advantages of the new design method are enhanced at smaller feature sizes: at 16nm the new gates outperform the classic ones in reliability, power, and PDP.

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Low-power and highly reliable logic gates transistor-level optimizations

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