Low-power reliable nano adders

Addition is a common arithmetic operation in a wide variety of digital applications. Full adder (FA) cells are used in many arithmetic operations and are crucial in both central and floating-point units. They are also used extensively for cache as well as for memory address calculations. The soaring demand for mobile electronic devices such as portable computers, smart phones, and tablets necessitates power-efficient very-large-scale integration (VLSI) circuits. As FA cells are on the critical path, they determine the system’s overall performance. That is why designing faster and low-power FAs was the main driving force behind many of the reported results [1-4].