Abstract
In this paper, we present mathematical models of the failure probabilities of individual MOS transistors. We use the models to characterize the failures of a few common CMOS logic cells. The failure models for the cells accurately represent the probabilities by considering the transistor dimensions, the supply voltage level, the input voltage level, and the variations in threshold voltages. We also demonstrate how the models can be utilized to analyze the sensitivities of cells' failure probabilities to their transistor sizes. Using scatter-plots, we observed a strong correlation between individual transistors' probabilities and their sizes; the cells, however, exhibited mixed sets of correlations, i.e., strong and weak. The presented modeling and analysis techniques are applicable to any CMOS logic cell operating between nearthreshold and nominal voltages.
Original language | English |
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Title of host publication | Proceedings - 2016 3rd International Conference on Mathematics and Computers in Sciences and in Industry, MCSI 2016 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 94-99 |
Number of pages | 6 |
ISBN (Electronic) | 9781509009732 |
DOIs | |
Publication status | Published - Jan 11 2017 |
Event | 3rd International Conference on Mathematics and Computers in Sciences and in Industry, MCSI 2016 - Chania, Greece Duration: Aug 27 2016 → Aug 29 2016 |
Other
Other | 3rd International Conference on Mathematics and Computers in Sciences and in Industry, MCSI 2016 |
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Country/Territory | Greece |
City | Chania |
Period | 8/27/16 → 8/29/16 |
Keywords
- CMOS logic cell
- CMOS logic gate
- Failure probability
- Mathematical model
- Reliability
- Sensitivity analysis
- Transistor sizing
ASJC Scopus subject areas
- Management Information Systems
- Computer Networks and Communications
- Computer Science Applications
- Computer Vision and Pattern Recognition
- Hardware and Architecture
- Control and Systems Engineering
- Control and Optimization
- Modelling and Simulation