Modeling the probabilities of failures of 22 nm CMOS logic cells

Azam Beg

doi:10.1109/MCSI.2016.20

Modeling the probabilities of failures of 22 nm CMOS logic cells

Azam Beg

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

In this paper, we present mathematical models of the failure probabilities of individual MOS transistors. We use the models to characterize the failures of a few common CMOS logic cells. The failure models for the cells accurately represent the probabilities by considering the transistor dimensions, the supply voltage level, the input voltage level, and the variations in threshold voltages. We also demonstrate how the models can be utilized to analyze the sensitivities of cells' failure probabilities to their transistor sizes. Using scatter-plots, we observed a strong correlation between individual transistors' probabilities and their sizes; the cells, however, exhibited mixed sets of correlations, i.e., strong and weak. The presented modeling and analysis techniques are applicable to any CMOS logic cell operating between nearthreshold and nominal voltages.

Original language	English
Title of host publication	Proceedings - 2016 3rd International Conference on Mathematics and Computers in Sciences and in Industry, MCSI 2016
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	94-99
Number of pages	6
ISBN (Electronic)	9781509009732
DOIs	https://doi.org/10.1109/MCSI.2016.20
Publication status	Published - Jan 11 2017
Event	3rd International Conference on Mathematics and Computers in Sciences and in Industry, MCSI 2016 - Chania, Greece Duration: Aug 27 2016 → Aug 29 2016

Other

Other	3rd International Conference on Mathematics and Computers in Sciences and in Industry, MCSI 2016
Country/Territory	Greece
City	Chania
Period	8/27/16 → 8/29/16

Keywords

CMOS logic cell
CMOS logic gate
Failure probability
Mathematical model
Reliability
Sensitivity analysis
Transistor sizing

ASJC Scopus subject areas

Management Information Systems
Computer Networks and Communications
Computer Science Applications
Computer Vision and Pattern Recognition
Hardware and Architecture
Control and Systems Engineering
Control and Optimization
Modelling and Simulation

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10.1109/MCSI.2016.20

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Beg, A 2017, Modeling the probabilities of failures of 22 nm CMOS logic cells. in Proceedings - 2016 3rd International Conference on Mathematics and Computers in Sciences and in Industry, MCSI 2016., 7815128, Institute of Electrical and Electronics Engineers Inc., pp. 94-99, 3rd International Conference on Mathematics and Computers in Sciences and in Industry, MCSI 2016, Chania, Greece, 8/27/16. https://doi.org/10.1109/MCSI.2016.20

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title = "Modeling the probabilities of failures of 22 nm CMOS logic cells",

abstract = "In this paper, we present mathematical models of the failure probabilities of individual MOS transistors. We use the models to characterize the failures of a few common CMOS logic cells. The failure models for the cells accurately represent the probabilities by considering the transistor dimensions, the supply voltage level, the input voltage level, and the variations in threshold voltages. We also demonstrate how the models can be utilized to analyze the sensitivities of cells' failure probabilities to their transistor sizes. Using scatter-plots, we observed a strong correlation between individual transistors' probabilities and their sizes; the cells, however, exhibited mixed sets of correlations, i.e., strong and weak. The presented modeling and analysis techniques are applicable to any CMOS logic cell operating between nearthreshold and nominal voltages.",

keywords = "CMOS logic cell, CMOS logic gate, Failure probability, Mathematical model, Reliability, Sensitivity analysis, Transistor sizing",

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booktitle = "Proceedings - 2016 3rd International Conference on Mathematics and Computers in Sciences and in Industry, MCSI 2016",

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PY - 2017/1/11

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N2 - In this paper, we present mathematical models of the failure probabilities of individual MOS transistors. We use the models to characterize the failures of a few common CMOS logic cells. The failure models for the cells accurately represent the probabilities by considering the transistor dimensions, the supply voltage level, the input voltage level, and the variations in threshold voltages. We also demonstrate how the models can be utilized to analyze the sensitivities of cells' failure probabilities to their transistor sizes. Using scatter-plots, we observed a strong correlation between individual transistors' probabilities and their sizes; the cells, however, exhibited mixed sets of correlations, i.e., strong and weak. The presented modeling and analysis techniques are applicable to any CMOS logic cell operating between nearthreshold and nominal voltages.

AB - In this paper, we present mathematical models of the failure probabilities of individual MOS transistors. We use the models to characterize the failures of a few common CMOS logic cells. The failure models for the cells accurately represent the probabilities by considering the transistor dimensions, the supply voltage level, the input voltage level, and the variations in threshold voltages. We also demonstrate how the models can be utilized to analyze the sensitivities of cells' failure probabilities to their transistor sizes. Using scatter-plots, we observed a strong correlation between individual transistors' probabilities and their sizes; the cells, however, exhibited mixed sets of correlations, i.e., strong and weak. The presented modeling and analysis techniques are applicable to any CMOS logic cell operating between nearthreshold and nominal voltages.

KW - CMOS logic cell

KW - CMOS logic gate

KW - Failure probability

KW - Mathematical model

KW - Reliability

KW - Sensitivity analysis

KW - Transistor sizing

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BT - Proceedings - 2016 3rd International Conference on Mathematics and Computers in Sciences and in Industry, MCSI 2016

PB - Institute of Electrical and Electronics Engineers Inc.

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Y2 - 27 August 2016 through 29 August 2016

ER -

Modeling the probabilities of failures of 22 nm CMOS logic cells

Abstract

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Keywords

ASJC Scopus subject areas

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