TY - GEN
T1 - Monte Carlo analysis of the static noise margins for CMOS gates in predictive technology models
AU - Acharya, N. V.
AU - Raju, J. L.
AU - Kumar, A.
AU - Tache, M.
AU - Beiu, V.
PY - 2013
Y1 - 2013
N2 - The latest results on biasing (upsizing) the gate lengths of CMOS transistors implemented in advanced technologies have identified optimum lengths which allow maximizing the static noise margins (SNMs). The optimum lengths for nMOS and pMOS transistors were determined analytically, based on BSIM4v4.7.0 equations for the threshold voltage. Further, it has been shown through simulations that designs using such optimum lengths exhibit better performances than those obtained using classical design methods (minimum length transistors). In this paper, we will present for the first time detailed Monte Carlo (MC) simulations for estimating the SNMs of XOR-2 and MAJ-3 CMOS gates when implemented in 22nm predictive technology models (PTM). These support the claim that the SNMs of CMOS gates using optimally sized transistors are significantly (about twice) better than the SNMs of classically sized CMOS gates, for any input combinations.
AB - The latest results on biasing (upsizing) the gate lengths of CMOS transistors implemented in advanced technologies have identified optimum lengths which allow maximizing the static noise margins (SNMs). The optimum lengths for nMOS and pMOS transistors were determined analytically, based on BSIM4v4.7.0 equations for the threshold voltage. Further, it has been shown through simulations that designs using such optimum lengths exhibit better performances than those obtained using classical design methods (minimum length transistors). In this paper, we will present for the first time detailed Monte Carlo (MC) simulations for estimating the SNMs of XOR-2 and MAJ-3 CMOS gates when implemented in 22nm predictive technology models (PTM). These support the claim that the SNMs of CMOS gates using optimally sized transistors are significantly (about twice) better than the SNMs of classically sized CMOS gates, for any input combinations.
KW - CMOS
KW - Monte Carlo (MC)
KW - predictive technology model (PTM)
KW - static noise margin (SNM)
UR - http://www.scopus.com/inward/record.url?scp=84893544824&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84893544824&partnerID=8YFLogxK
U2 - 10.1109/IEEEGCC.2013.6705739
DO - 10.1109/IEEEGCC.2013.6705739
M3 - Conference contribution
AN - SCOPUS:84893544824
SN - 9781479907243
T3 - 2013 7th IEEE GCC Conference and Exhibition, GCC 2013
SP - 5
EP - 10
BT - 2013 7th IEEE GCC Conference and Exhibition, GCC 2013
T2 - 2013 7th IEEE GCC Conference and Exhibition, GCC 2013
Y2 - 17 November 2013 through 20 November 2013
ER -