Monte Carlo analysis of the static noise margins for CMOS gates in predictive technology models

N. V. Acharya, J. L. Raju, A. Kumar, M. Tache, V. Beiu

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    4 Citations (Scopus)

    Abstract

    The latest results on biasing (upsizing) the gate lengths of CMOS transistors implemented in advanced technologies have identified optimum lengths which allow maximizing the static noise margins (SNMs). The optimum lengths for nMOS and pMOS transistors were determined analytically, based on BSIM4v4.7.0 equations for the threshold voltage. Further, it has been shown through simulations that designs using such optimum lengths exhibit better performances than those obtained using classical design methods (minimum length transistors). In this paper, we will present for the first time detailed Monte Carlo (MC) simulations for estimating the SNMs of XOR-2 and MAJ-3 CMOS gates when implemented in 22nm predictive technology models (PTM). These support the claim that the SNMs of CMOS gates using optimally sized transistors are significantly (about twice) better than the SNMs of classically sized CMOS gates, for any input combinations.

    Original languageEnglish
    Title of host publication2013 7th IEEE GCC Conference and Exhibition, GCC 2013
    Pages5-10
    Number of pages6
    DOIs
    Publication statusPublished - 2013
    Event2013 7th IEEE GCC Conference and Exhibition, GCC 2013 - Doha, Qatar
    Duration: Nov 17 2013Nov 20 2013

    Publication series

    Name2013 7th IEEE GCC Conference and Exhibition, GCC 2013

    Other

    Other2013 7th IEEE GCC Conference and Exhibition, GCC 2013
    Country/TerritoryQatar
    CityDoha
    Period11/17/1311/20/13

    Keywords

    • CMOS
    • Monte Carlo (MC)
    • predictive technology model (PTM)
    • static noise margin (SNM)

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering

    Fingerprint

    Dive into the research topics of 'Monte Carlo analysis of the static noise margins for CMOS gates in predictive technology models'. Together they form a unique fingerprint.

    Cite this