TY - GEN
T1 - Multiplexing schemes for cost-effective fault-tolerance
AU - Roy, Sandip
AU - Beiu, Valeriu
PY - 2004
Y1 - 2004
N2 - Motivated by the need for cost-effective fault-tolerant nano architectures, we explore von Neumann multiplexing (vN-MUX) at small and very small redundancy factors. We present a novel analysis of vN-MUX of 3-input majority gates (MAJ-3), using combinatorial arguments to exactly determine performance. We show that MAJ-3 vN-MUX performs very well when compared to other redundancy schemes, increasing the allowed device error probability by four orders of magnitude (for small redundancy factors). We describe in detail an extension, called MAJ-3 vN-MUX(N,k), that contributes up to four more orders of magnitude, by excluding superfluous restorative stages for very small redundancy factors. We also analytically determine the performance of MAJ-3 vN-MUX for large redundancy factors, finding that the maximum tolerable gate failure probability is 0.0197 (in contrast to 0.0107 for NAND-2 vN-MUX).
AB - Motivated by the need for cost-effective fault-tolerant nano architectures, we explore von Neumann multiplexing (vN-MUX) at small and very small redundancy factors. We present a novel analysis of vN-MUX of 3-input majority gates (MAJ-3), using combinatorial arguments to exactly determine performance. We show that MAJ-3 vN-MUX performs very well when compared to other redundancy schemes, increasing the allowed device error probability by four orders of magnitude (for small redundancy factors). We describe in detail an extension, called MAJ-3 vN-MUX(N,k), that contributes up to four more orders of magnitude, by excluding superfluous restorative stages for very small redundancy factors. We also analytically determine the performance of MAJ-3 vN-MUX for large redundancy factors, finding that the maximum tolerable gate failure probability is 0.0197 (in contrast to 0.0107 for NAND-2 vN-MUX).
KW - Architecture
KW - Fault-tolerance
KW - Majority logic circuits
KW - Multiplexing
UR - http://www.scopus.com/inward/record.url?scp=20344383007&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=20344383007&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:20344383007
SN - 0780385365
SN - 9780780385368
T3 - 2004 4th IEEE Conference on Nanotechnology
SP - 589
EP - 592
BT - 2004 4th IEEE Conference on Nanotechnology
T2 - 2004 4th IEEE Conference on Nanotechnology
Y2 - 16 August 2004 through 19 August 2004
ER -