This paper investigates multiplexing schemes in single-electron technology (SET). The study focuses on the behavior of two multiplexing schemes in combination with gates subject to geometric variations affecting their elementary components (capacitors). The two schemes under investigation are MAJORITY- and NAND-multiplexing. First, the elementary gates are compared in terms of their intrinsic probability of failure with respect to variations. Secondly, the two multiplexing schemes are weighted against the reliability enhancements they are able to bring into the system. This study gives a deeper insight into the behavior of fault-tolerant multiplexing schemes. It also shows how the logic styles, as well as the technology, could affect the overall reliability of a multiplexed system. Such aspects have been normally neglected, but should be carefully considered in the design of future nanoarchitectures.