TY - JOUR
T1 - Multithreaded and reconvergent aware algorithms for accurate digital circuits reliability estimation
AU - Ibrahim, Walid
AU - Ibrahim, Hazem
N1 - Funding Information:
Manuscript received January 2, 2018; revised March 19, 2018 and June 27, 2018; accepted October 2, 2018. Date of publication November 15, 2018; date of current version May 28, 2019. This work was supported by United Arab Emirates University under Grant #31T057, entitled “Parallel Algorithm for Accurate and Efficient Estimation of Logic Circuits Reliability Bounds.” Associate Editor: Y. Deng. (Corresponding author: Walid Ibrahim.) W. Ibrahim is with the United Arab Emirates University, Al Ain, United Arab Emirates, Al Ain 15551, UAE (e-mail:,walidibr@uaeu.ac.ae).
Publisher Copyright:
© 1963-2012 IEEE.
PY - 2019/6
Y1 - 2019/6
N2 - Until recently, reliability was not considered to be a major design concern for circuit designers, except in the case of space and mission critical applications. However, the aggressive scaling of CMOS devices has significantly affected their reliable operation. Several schemes have been used for mitigating the scaling effects and maintaining the reliability above a certain threshold. Many of these schemes rely on incorporating different types of redundancy at the device, gate, and system level, which inevitably affect the area, power, and delay parameters. To optimize the tradeoff between these conflicting parameters, an accurate and efficient reliability EDA tool is needed. Such a tool would help circuit designers compare different reliability schemes and select the one that achieves the target reliability margins while having minimum impact on the other design parameters. However, the enormous size and the complexity of today's logic circuits make accurate calculation of the circuit's reliability a very challenging and time-consuming process. This paper introduces a novel, accurate, and efficient algorithm for circuit reliability estimation. The algorithm improves accuracy by taking the effect of reconvergent fan-out nodes into consideration, while improving efficiency by implementing a multithreaded approach for node evaluation. Simulation results show that the proposed algorithm is efficient and more accurate than other reliability estimation algorithms currently proposed in the literature.
AB - Until recently, reliability was not considered to be a major design concern for circuit designers, except in the case of space and mission critical applications. However, the aggressive scaling of CMOS devices has significantly affected their reliable operation. Several schemes have been used for mitigating the scaling effects and maintaining the reliability above a certain threshold. Many of these schemes rely on incorporating different types of redundancy at the device, gate, and system level, which inevitably affect the area, power, and delay parameters. To optimize the tradeoff between these conflicting parameters, an accurate and efficient reliability EDA tool is needed. Such a tool would help circuit designers compare different reliability schemes and select the one that achieves the target reliability margins while having minimum impact on the other design parameters. However, the enormous size and the complexity of today's logic circuits make accurate calculation of the circuit's reliability a very challenging and time-consuming process. This paper introduces a novel, accurate, and efficient algorithm for circuit reliability estimation. The algorithm improves accuracy by taking the effect of reconvergent fan-out nodes into consideration, while improving efficiency by implementing a multithreaded approach for node evaluation. Simulation results show that the proposed algorithm is efficient and more accurate than other reliability estimation algorithms currently proposed in the literature.
KW - Design automation
KW - fault tolerance
KW - heuristic algorithms
KW - logic circuits
KW - parallel processing
KW - reliability
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U2 - 10.1109/TR.2018.2876475
DO - 10.1109/TR.2018.2876475
M3 - Article
AN - SCOPUS:85056585052
SN - 0018-9529
VL - 68
SP - 514
EP - 525
JO - IEEE Transactions on Reliability
JF - IEEE Transactions on Reliability
IS - 2
M1 - 8536491
ER -