These days, computer-based image registration techniques are increasingly being used in the area of medical imaging as they offer significant benefits for aligning different images together and for visualizing their combined images. However, these techniques require an enormous amount of computation time due to the high resolution and complex nature of the medical images. We propose to alleviate this problem by using a dedicated Network-on-Chip (NoC)-based hardware platform for image registration. This paper describes a novel technique for field-programmable gate array (FPGA) implementation of the B-Spline-based free form deformation (FFD) algorithm, i.e., a widely used algorithm for modeling geometric shapes in a computerized environment. For performance enhancement, we have utilized a lightweight circuit-switched NoC architecture, which is adaptable to most FPGAs. The design description is captured in the Verilog language and implemented using the Xilinx XC2v6000 device at 37MHz. The proposed design is parameterizable at the compile time and supports a wide range of the image resolutions and computational precisions. The experimental results have shown a significant improvement in performance when compared with the other existing hardware implementations of the B-spline-based FFD algorithm.
- medical imaging
- network-on-chip architectures
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering