Novel heuristic and genetic algorithms for the VLSI test coverage problem

Validation of microprocessor designs is one of the most complex and expensive tasks in today's system-on-chip development process. Conditions to be validated are identified by the architects, the designers, and the validation team. Testing for these conditions is a must for the processor to tape out especially these conditions with high priorities. A significant bottleneck in the validation process of such systems is that not enough time is normally given to the final coverage phase and computing cycles becomes very precious resource. Thus, intelligent selection of test-cases that achieves the best coverage using the minimum number of computing cycles is crucial for on time tape out. This paper presents two novel techniques for testcase selection and condition coverage. The proposed techniques make two important contributions. First, it addresses the generalization of covering problems to partial covering. Second, it finds a good set of test-cases that fulfills the target coverage under different scenarios, while taking into considerations operations priority, and computing cycles required by each test-case.