On pedagogy of nanometric circuit reliability

    Research output: Contribution to journalArticlepeer-review

    2 Citations (Scopus)


    Fast-shrinking dimensions of semiconductor devices are expected to reach sub-10 nm scale in a few years. Although smaller in size and lower in power consumption than today's CMOS devices, the nanoscaled devices are much less reliable due to manufacturing imperfections (hard errors), and noise and radiation-induced faults (soft errors). Consequently, in addition to timing, area, and power, the reliability has to become a new design criterion. This also means that the topic of reliability has to be incorporated into the circuit design curriculum. In this paper, we propose a course on circuit reliability. We also present in detail, an automated tool for calculation of reliability which could be incorporated into the course as a means for active learning.

    Original languageEnglish
    Pages (from-to)762-778
    Number of pages17
    JournalJournal of Supercomputing
    Issue number2
    Publication statusPublished - Feb 2012


    • Active learning
    • Computer-aided design (CAD)
    • Engineering curriculum
    • Fault tolerance
    • Nano-architecture
    • Nano-circuits
    • Probability of failure
    • Probability transfer matrix (PTM)
    • Reliability
    • Teaching tool

    ASJC Scopus subject areas

    • Software
    • Theoretical Computer Science
    • Information Systems
    • Hardware and Architecture


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