This paper investigates the behavior of multiplexing schemes in combination with elementary gates. The two schemes under investigation are MAJORITY- and NAND-multiplexing. The simulation results are for single-electron technology (SET), where the elementary components of the gates (capacitors in the case of capacitive-SET) are subjected to geometric variations. First, the elementary gates are compared in terms of their intrinsic probability of failure with respect to variations. Secondly, the two multiplexing schemes are weighted against the reliability enhancements they are able to bring into the system. This study gives insights into the behavior of fault-tolerant multiplexing schemes and shows how the logic styles, as well as the technology, could affect the overall reliability of a multiplexed system. Such aspects should be carefully weighted for the design of future nano-architectures.