On single electron technology full adders

Mawahib Sulieman, Valeriu Beiu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)


This paper reviews several full adder (FA) designs in single electron technology (SET). In addition to the structure and size already reported for these SET FAs, this paper will provide a quantitative and qualitative comparison in terms of delay, power dissipation, and sensitivity to (process) variations - for the first time. This will allow for a better understanding of the advantages and disadvantages of each solution. A new SET FA design, based on capacitive SET threshold logic gates, will also be described and compared with the other SET FAs.

Original languageEnglish
Title of host publication2004 4th IEEE Conference on Nanotechnology
Number of pages4
Publication statusPublished - 2004
Externally publishedYes
Event2004 4th IEEE Conference on Nanotechnology - Munich, Germany
Duration: Aug 16 2004Aug 19 2004

Publication series

Name2004 4th IEEE Conference on Nanotechnology


Other2004 4th IEEE Conference on Nanotechnology


  • Failure analysis
  • Full adders
  • Power
  • Single electron technology
  • Threshold logic
  • Variations

ASJC Scopus subject areas

  • General Engineering


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