TY - GEN
T1 - On single electron technology full adders
AU - Sulieman, Mawahib
AU - Beiu, Valeriu
PY - 2004
Y1 - 2004
N2 - This paper reviews several full adder (FA) designs in single electron technology (SET). In addition to the structure and size already reported for these SET FAs, this paper will provide a quantitative and qualitative comparison in terms of delay, power dissipation, and sensitivity to (process) variations - for the first time. This will allow for a better understanding of the advantages and disadvantages of each solution. A new SET FA design, based on capacitive SET threshold logic gates, will also be described and compared with the other SET FAs.
AB - This paper reviews several full adder (FA) designs in single electron technology (SET). In addition to the structure and size already reported for these SET FAs, this paper will provide a quantitative and qualitative comparison in terms of delay, power dissipation, and sensitivity to (process) variations - for the first time. This will allow for a better understanding of the advantages and disadvantages of each solution. A new SET FA design, based on capacitive SET threshold logic gates, will also be described and compared with the other SET FAs.
KW - Failure analysis
KW - Full adders
KW - Power
KW - Single electron technology
KW - Threshold logic
KW - Variations
UR - http://www.scopus.com/inward/record.url?scp=20344387870&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=20344387870&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:20344387870
SN - 0780385365
T3 - 2004 4th IEEE Conference on Nanotechnology
SP - 317
EP - 320
BT - 2004 4th IEEE Conference on Nanotechnology
T2 - 2004 4th IEEE Conference on Nanotechnology
Y2 - 16 August 2004 through 19 August 2004
ER -