On single-electron technology full adders

Mawahib H. Sulieman; Valeriu Beiu

doi:10.1109/TNANO.2005.858609

On single-electron technology full adders

Mawahib H. Sulieman, Valeriu Beiu

Research output: Contribution to journal › Article › peer-review

39 Citations (Scopus)

Abstract

This paper reviews several full adder (FA) designs in single-electron technology (SET). In addition to the structure and size (i.e., number of devices), this paper tries to provide a quantitative and qualitative comparison in terms of delay, sensitivity to (process) variations, and complexity of the design. This will allow for a better understanding of the advantages and disadvantages of each solution. An optimization of an SET FA (combining one of the SET FAs with a static buffer), together with a new SET FA design (based on capacitive SET threshold logic gates), will also be described and compared with the other SET FAs.

Original language	English
Pages (from-to)	669-680
Number of pages	12
Journal	IEEE Transactions on Nanotechnology
Volume	4
Issue number	6
DOIs	https://doi.org/10.1109/TNANO.2005.858609
Publication status	Published - Nov 2005

Keywords

Full adders (FAs)
Sensitivity to variations
Single-electron technology (SET)
Threshold logic

ASJC Scopus subject areas

Computer Science Applications
Electrical and Electronic Engineering

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10.1109/TNANO.2005.858609

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KW - Sensitivity to variations

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KW - Threshold logic

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On single-electron technology full adders

Abstract

Keywords

ASJC Scopus subject areas

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