On single-electron technology full adders

Mawahib H. Sulieman, Valeriu Beiu

    Research output: Contribution to journalArticlepeer-review

    40 Citations (Scopus)


    This paper reviews several full adder (FA) designs in single-electron technology (SET). In addition to the structure and size (i.e., number of devices), this paper tries to provide a quantitative and qualitative comparison in terms of delay, sensitivity to (process) variations, and complexity of the design. This will allow for a better understanding of the advantages and disadvantages of each solution. An optimization of an SET FA (combining one of the SET FAs with a static buffer), together with a new SET FA design (based on capacitive SET threshold logic gates), will also be described and compared with the other SET FAs.

    Original languageEnglish
    Pages (from-to)669-680
    Number of pages12
    JournalIEEE Transactions on Nanotechnology
    Issue number6
    Publication statusPublished - Nov 2005


    • Full adders (FAs)
    • Sensitivity to variations
    • Single-electron technology (SET)
    • Threshold logic

    ASJC Scopus subject areas

    • Computer Science Applications
    • Electrical and Electronic Engineering


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