On SRAM bit-cells once again

Mihai Tache, Fekri Kharbash, Valeriu Beiu

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Abstract

    Noises and variations are ubiquitous, but are still being ill-understood and in most cases treated simplistically, leading in most cases to substantial overdesign costs. A novel reliability-centric design method based on unconventionally sizing transistors has been suggested lately. In this paper our aim is to design, simulate, and compare the benefits of unconventional sizing when applied to ultra-low voltage (ULV) SRAM cells. We will show that unconventionally sized SRAM cells achieve higher SNM's than classically sized SRAM cells (hence it is to be expected that they will work correctly at lower supply voltages).

    Original languageEnglish
    Title of host publication2014 10th International Conference on Innovations in Information Technology, IIT 2014
    PublisherInstitute of Electrical and Electronics Engineers Inc.
    Pages80-83
    Number of pages4
    ISBN (Electronic)9781479972128
    DOIs
    Publication statusPublished - Dec 16 2014
    Event2014 10th International Conference on Innovations in Information Technology, IIT 2014 - Abu Dhabi, Al-Ain, United Arab Emirates
    Duration: Nov 9 2014Nov 11 2014

    Publication series

    Name2014 10th International Conference on Innovations in Information Technology, IIT 2014

    Other

    Other2014 10th International Conference on Innovations in Information Technology, IIT 2014
    Country/TerritoryUnited Arab Emirates
    CityAbu Dhabi, Al-Ain
    Period11/9/1411/11/14

    Keywords

    • CMOS
    • SRAM
    • reliability
    • static noise margin (SNM)
    • transistor sizing

    ASJC Scopus subject areas

    • Computer Science Applications
    • Information Systems
    • Software

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