On the circuit and VLSI complexity of threshold gate COMPARISON

The paper overviews recent developments concerning optimal (from the point of view of size and depth) implementations of COMPARISON using threshold gates. We detail a class of solutions which also covers other particular solutions, and spans from constant to logarithmic depths. These theoretical circuit complexity results are extended to VLSI complexity ones, having practical applications to: (i) hardware implementations of integrated circuits; (ii) VLSI-friendly neural learning algorithms (i.e., constructive, or ontogenetic algorithms); and (iii) synthesis methods for mixed digital/analog technologies. In order to estimate the area (A) and the delay (T), as well as the classical AT², we make use of the following 'cost functions': (i) the connectivity (i.e., sum of fan-ins) and the number-of- bits for representing the weights and thresholds are used as closer approximations of the area; while (ii) the fan-ins and the length of the wires are used for closer estimates of the delay. Such approximations will allow us to compare several solutions - which present very interesting fan- in-dependent depth-size and area-delay tradeoffs - with respect to AT².