On the design of SET adders

Mawahib Sulieman; Valeriu Beiu

On the design of SET adders

Mawahib Sulieman, Valeriu Beiu

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Single-Electron-Technology (SET) is one of the future technologies distinguished by its small and low power devices. SET also provides simple and elegant solutions for threshold logic gates (TLG's). This paper presents the design of an optimal TLG adder implemented in SET. It provides a detailed procedure for designing capacitive -input SET TLG's for building the adder. The paper also presents design details and characteristics (delay and power dissipation) of a 16-bit Kogge-Stone SET adder.

Original language	English
Title of host publication	2004 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2004
Editors	M. Laudon, B. Romanowicz
Pages	169-172
Number of pages	4
Publication status	Published - 2004
Externally published	Yes
Event	2004 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2004 - Boston, MA, United States Duration: Mar 7 2004 → Mar 11 2004

Publication series

Name	2004 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2004
Volume	3

Other

Other	2004 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2004
Country/Territory	United States
City	Boston, MA
Period	3/7/04 → 3/11/04

Keywords

Adders
Single-electron technology
Threshold logic

ASJC Scopus subject areas

General Engineering

Cite this

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title = "On the design of SET adders",

abstract = "Single-Electron-Technology (SET) is one of the future technologies distinguished by its small and low power devices. SET also provides simple and elegant solutions for threshold logic gates (TLG's). This paper presents the design of an optimal TLG adder implemented in SET. It provides a detailed procedure for designing capacitive -input SET TLG's for building the adder. The paper also presents design details and characteristics (delay and power dissipation) of a 16-bit Kogge-Stone SET adder.",

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year = "2004",

language = "English",

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series = "2004 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2004",

pages = "169--172",

editor = "M. Laudon and B. Romanowicz",

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note = "2004 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2004 ; Conference date: 07-03-2004 Through 11-03-2004",

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AU - Sulieman, Mawahib

AU - Beiu, Valeriu

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AB - Single-Electron-Technology (SET) is one of the future technologies distinguished by its small and low power devices. SET also provides simple and elegant solutions for threshold logic gates (TLG's). This paper presents the design of an optimal TLG adder implemented in SET. It provides a detailed procedure for designing capacitive -input SET TLG's for building the adder. The paper also presents design details and characteristics (delay and power dissipation) of a 16-bit Kogge-Stone SET adder.

KW - Adders

KW - Single-electron technology

KW - Threshold logic

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M3 - Conference contribution

AN - SCOPUS:6344233507

SN - 0972842276

T3 - 2004 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2004

SP - 169

EP - 172

BT - 2004 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2004

A2 - Laudon, M.

A2 - Romanowicz, B.

T2 - 2004 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2004

Y2 - 7 March 2004 through 11 March 2004

ER -

On the design of SET adders

Abstract

Publication series

Other

Keywords

ASJC Scopus subject areas

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