On upsizing length and noise margins

Valeriu Beiu; Mihai Tache; Walid Ibrahim; Fekri Kharbash; Massimo Alioto

doi:10.1109/SMICND.2013.6688659

On upsizing length and noise margins

Valeriu Beiu, Mihai Tache, Walid Ibrahim, Fekri Kharbash, Massimo Alioto

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

7 Citations (Scopus)

Abstract

This paper revisits a transistor sizing method for CMOS gates, which relies on upsizing the length (L) and balancing the voltage transfer characteristics for maximizing the static noise margins (SNM's). It leads to highly reliable gates, able to operate over the whole voltage range. The improvements are: (i) calculating the threshold voltage (V_th) exactly (leading to exact L's); (ii) more accurate SNM estimations (using the maximum square method); (iii) sizing the widths for single input transitions. Simulations for INV, NAND-2, and NOR-2 show that V_th and L change by ∼2%, while SNM's increase by 30% with power and energy being reduced 10× and 20× respectively.

Original language	English
Title of host publication	CAS 2013 Proceedings - 2013 International Semiconductor Conference
Pages	219-222
Number of pages	4
DOIs	https://doi.org/10.1109/SMICND.2013.6688659
Publication status	Published - 2013
Event	36th International Semiconductor Conference, CAS 2013 - Sinaia, Romania Duration: Oct 14 2013 → Oct 16 2013

Publication series

Name	Proceedings of the International Semiconductor Conference, CAS
Volume	2

Conference

Conference	36th International Semiconductor Conference, CAS 2013
Country/Territory	Romania
City	Sinaia
Period	10/14/13 → 10/16/13

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering

Access to Document

10.1109/SMICND.2013.6688659

Cite this

Beiu, V, Tache, M, Ibrahim, W , Kharbash, F & Alioto, M 2013, On upsizing length and noise margins. in CAS 2013 Proceedings - 2013 International Semiconductor Conference., 6688659, Proceedings of the International Semiconductor Conference, CAS, vol. 2, pp. 219-222, 36th International Semiconductor Conference, CAS 2013, Sinaia, Romania, 10/14/13. https://doi.org/10.1109/SMICND.2013.6688659

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abstract = "This paper revisits a transistor sizing method for CMOS gates, which relies on upsizing the length (L) and balancing the voltage transfer characteristics for maximizing the static noise margins (SNM's). It leads to highly reliable gates, able to operate over the whole voltage range. The improvements are: (i) calculating the threshold voltage (Vth) exactly (leading to exact L's); (ii) more accurate SNM estimations (using the maximum square method); (iii) sizing the widths for single input transitions. Simulations for INV, NAND-2, and NOR-2 show that Vth and L change by ∼2%, while SNM's increase by 30% with power and energy being reduced 10× and 20× respectively.",

author = "Valeriu Beiu and Mihai Tache and Walid Ibrahim and Fekri Kharbash and Massimo Alioto",

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language = "English",

isbn = "9781467356701",

series = "Proceedings of the International Semiconductor Conference, CAS",

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AU - Beiu, Valeriu

AU - Tache, Mihai

AU - Ibrahim, Walid

AU - Kharbash, Fekri

AU - Alioto, Massimo

PY - 2013

Y1 - 2013

N2 - This paper revisits a transistor sizing method for CMOS gates, which relies on upsizing the length (L) and balancing the voltage transfer characteristics for maximizing the static noise margins (SNM's). It leads to highly reliable gates, able to operate over the whole voltage range. The improvements are: (i) calculating the threshold voltage (Vth) exactly (leading to exact L's); (ii) more accurate SNM estimations (using the maximum square method); (iii) sizing the widths for single input transitions. Simulations for INV, NAND-2, and NOR-2 show that Vth and L change by ∼2%, while SNM's increase by 30% with power and energy being reduced 10× and 20× respectively.

AB - This paper revisits a transistor sizing method for CMOS gates, which relies on upsizing the length (L) and balancing the voltage transfer characteristics for maximizing the static noise margins (SNM's). It leads to highly reliable gates, able to operate over the whole voltage range. The improvements are: (i) calculating the threshold voltage (Vth) exactly (leading to exact L's); (ii) more accurate SNM estimations (using the maximum square method); (iii) sizing the widths for single input transitions. Simulations for INV, NAND-2, and NOR-2 show that Vth and L change by ∼2%, while SNM's increase by 30% with power and energy being reduced 10× and 20× respectively.

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DO - 10.1109/SMICND.2013.6688659

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T3 - Proceedings of the International Semiconductor Conference, CAS

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BT - CAS 2013 Proceedings - 2013 International Semiconductor Conference

T2 - 36th International Semiconductor Conference, CAS 2013

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On upsizing length and noise margins

Abstract

Publication series

Conference

ASJC Scopus subject areas

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