On upsizing length and noise margins

Valeriu Beiu, Mihai Tache, Walid Ibrahim, Fekri Kharbash, Massimo Alioto

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    7 Citations (Scopus)


    This paper revisits a transistor sizing method for CMOS gates, which relies on upsizing the length (L) and balancing the voltage transfer characteristics for maximizing the static noise margins (SNM's). It leads to highly reliable gates, able to operate over the whole voltage range. The improvements are: (i) calculating the threshold voltage (Vth) exactly (leading to exact L's); (ii) more accurate SNM estimations (using the maximum square method); (iii) sizing the widths for single input transitions. Simulations for INV, NAND-2, and NOR-2 show that Vth and L change by ∼2%, while SNM's increase by 30% with power and energy being reduced 10× and 20× respectively.

    Original languageEnglish
    Title of host publicationCAS 2013 Proceedings - 2013 International Semiconductor Conference
    Number of pages4
    Publication statusPublished - 2013
    Event36th International Semiconductor Conference, CAS 2013 - Sinaia, Romania
    Duration: Oct 14 2013Oct 16 2013

    Publication series

    NameProceedings of the International Semiconductor Conference, CAS


    Conference36th International Semiconductor Conference, CAS 2013

    ASJC Scopus subject areas

    • Electronic, Optical and Magnetic Materials
    • Condensed Matter Physics
    • Electrical and Electronic Engineering


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