Abstract
In this paper, we present a multi-objective optimisation technique for transistor sizing in the variation-prone nanometric complementary metal-oxide semiconductor (CMOS) logic cells. To demonstrate the effectiveness of the technique, we have used the common figures-of-merit, such as power, energy, and static noise margin. By using examples of different logic cells, we have demonstrated how competing design goals can be tackled effectively. We show that concurrent improvements in multiple figures-of-merit are possible using the proposed method.
Original language | English |
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Pages (from-to) | 1120-1131 |
Number of pages | 12 |
Journal | International Journal of Electronics |
Volume | 104 |
Issue number | 7 |
DOIs | |
Publication status | Published - Jul 3 2017 |
Keywords
- CMOS technology
- combinational circuits
- genetic algorithms
- logic circuits
- multi-objective optimisation
- transistor sizing
ASJC Scopus subject areas
- Electrical and Electronic Engineering