Optimising nanometric CMOS logic cells for low-power, low-energy, and noise margin

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2 Citations (Scopus)


In this paper, we present a multi-objective optimisation technique for transistor sizing in the variation-prone nanometric complementary metal-oxide semiconductor (CMOS) logic cells. To demonstrate the effectiveness of the technique, we have used the common figures-of-merit, such as power, energy, and static noise margin. By using examples of different logic cells, we have demonstrated how competing design goals can be tackled effectively. We show that concurrent improvements in multiple figures-of-merit are possible using the proposed method.

Original languageEnglish
Pages (from-to)1120-1131
Number of pages12
JournalInternational Journal of Electronics
Issue number7
Publication statusPublished - Jul 3 2017


  • CMOS technology
  • combinational circuits
  • genetic algorithms
  • logic circuits
  • multi-objective optimisation
  • transistor sizing

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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