@inproceedings{31f91d42d3bb46889426e59a7a532ac7,
title = "Optimization of 22 nm logic gates for power-and-noise-margin and energy-and-noise-margin",
abstract = "In this paper, we propose a technique for concurrent optimization of CMOS logic gates for power-and-noise-margin and energy-and-noise-margin. The role of progressive sizing for performance enhancement of different gates has been expanded to cover other figures of merit, such as reliability, power, and energy. By using the examples of three- and four-input logic gates, we have demonstrated how multiple, yet conflicting design goals can be achieved. For example, one of our high-performance gates exhibited power savings of more than 30% while reducing the gate area by 39%. An important step of balancing the rise- and fall-times of output was also incorporated into the optimization setup. Our proposed methodology is scalable and can be used for optimizing larger logic blocks.",
keywords = "CMOS technology, Combinational circuits, Genetic algorithms, Logic circuits, Multi-objective optimization, Transistor sizing",
author = "Azam Beg and Rashad Ramzan and Amr Elchouemi",
note = "Funding Information: This work is partially supported by ADEC Award for Research Excellence (A2RE) 2015. Publisher Copyright: CSREA Press {\textcopyright}.; 2016 International Conference on Artificial Intelligence, ICAI 2016 - WORLDCOMP 2016 ; Conference date: 25-07-2016 Through 28-07-2016",
year = "2016",
language = "English",
series = "Proceedings of the 2016 International Conference on Artificial Intelligence, ICAI 2016 - WORLDCOMP 2016",
publisher = "CSREA Press",
pages = "314--318",
editor = "Arabnia, {Hamid R.} and {de la Fuente}, David and Roger Dziegiel and Kozerenko, {Elena B.} and LaMonica, {Peter M.} and Liuzzi, {Raymond A.} and Olivas, {Jose A.} and Todd Waskiewicz and George Jandieri and Solo, {Ashu M.G.} and Tinetti, {Fernando G.}",
booktitle = "Proceedings of the 2016 International Conference on Artificial Intelligence, ICAI 2016 - WORLDCOMP 2016",
}