Optimum reliability sizing for complementary metal oxide semiconductor gates

Walid Ibrahim, Valeriu Beiu, Azam Beg

    Research output: Contribution to journalArticlepeer-review

    18 Citations (Scopus)


    Introducing redundancy at the device-level has been proposed as the most effective way to improve reliability. With the remarkable reliability of the complementary metal oxide semiconductor (CMOS) transistors the semiconductor industry was able to fabricate, the research on device-level redundancy has reduced. However, the increasing sensitivity to noise and variations (due to the massive scaling) of the CMOS transistors has led to a revival of interest in device-level redundancy schemes during the last decade. In this paper, we introduce a novel transistor sizing method that can be used to significantly reduce the probability of failure of CMOS gates due to threshold voltage variations. The method has almost no impact on the occupied area. For a given reliability target, the proposed sizing method provides very large scale integration (VLSI) designers with several transistor sizing options which allow them to optimize the trade-off between reliability and the traditional power-area-delay design parameters. The simulation results reported in this paper will show that the proposed transistor sizing method can improve the reliabilities of classical INV, NAND-2, and NOR-2 CMOS gates by factors of more than $10 5, 10, and $10 10 respectively, while the area is increased by less than 50%.

    Original languageEnglish
    Article number6239638
    Pages (from-to)675-686
    Number of pages12
    JournalIEEE Transactions on Reliability
    Issue number3
    Publication statusPublished - 2012


    • Complementary metal oxide semiconductor gates
    • metal oxide semiconductor transistor
    • power delay product

    ASJC Scopus subject areas

    • Safety, Risk, Reliability and Quality
    • Electrical and Electronic Engineering


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