TY - JOUR
T1 - Optimum reliability sizing for complementary metal oxide semiconductor gates
AU - Ibrahim, Walid
AU - Beiu, Valeriu
AU - Beg, Azam
N1 - Funding Information:
Manuscript received July 31, 2011; revised January 11, 2012 and January 20, 2012; accepted January 26, 2012. Date of publication July 13, 2012; date of current version August 28, 2012. W. Ibrahim was supported by a Grant from the UAEU (number 3245). V. Beiu was supported by a Grant from the UAEU (number 1108-00451) entitled “Brain-inspired Interconnects for Nanoelectronics (BiIN),” and partly by a grant from Intel entitled “Ultra Low Power non-Boolean Systems.”. Associate Editor: J.-C. Lu.
PY - 2012
Y1 - 2012
N2 - Introducing redundancy at the device-level has been proposed as the most effective way to improve reliability. With the remarkable reliability of the complementary metal oxide semiconductor (CMOS) transistors the semiconductor industry was able to fabricate, the research on device-level redundancy has reduced. However, the increasing sensitivity to noise and variations (due to the massive scaling) of the CMOS transistors has led to a revival of interest in device-level redundancy schemes during the last decade. In this paper, we introduce a novel transistor sizing method that can be used to significantly reduce the probability of failure of CMOS gates due to threshold voltage variations. The method has almost no impact on the occupied area. For a given reliability target, the proposed sizing method provides very large scale integration (VLSI) designers with several transistor sizing options which allow them to optimize the trade-off between reliability and the traditional power-area-delay design parameters. The simulation results reported in this paper will show that the proposed transistor sizing method can improve the reliabilities of classical INV, NAND-2, and NOR-2 CMOS gates by factors of more than $10 5, 10, and $10 10 respectively, while the area is increased by less than 50%.
AB - Introducing redundancy at the device-level has been proposed as the most effective way to improve reliability. With the remarkable reliability of the complementary metal oxide semiconductor (CMOS) transistors the semiconductor industry was able to fabricate, the research on device-level redundancy has reduced. However, the increasing sensitivity to noise and variations (due to the massive scaling) of the CMOS transistors has led to a revival of interest in device-level redundancy schemes during the last decade. In this paper, we introduce a novel transistor sizing method that can be used to significantly reduce the probability of failure of CMOS gates due to threshold voltage variations. The method has almost no impact on the occupied area. For a given reliability target, the proposed sizing method provides very large scale integration (VLSI) designers with several transistor sizing options which allow them to optimize the trade-off between reliability and the traditional power-area-delay design parameters. The simulation results reported in this paper will show that the proposed transistor sizing method can improve the reliabilities of classical INV, NAND-2, and NOR-2 CMOS gates by factors of more than $10 5, 10, and $10 10 respectively, while the area is increased by less than 50%.
KW - Complementary metal oxide semiconductor gates
KW - metal oxide semiconductor transistor
KW - power delay product
UR - http://www.scopus.com/inward/record.url?scp=84865760150&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84865760150&partnerID=8YFLogxK
U2 - 10.1109/TR.2012.2206249
DO - 10.1109/TR.2012.2206249
M3 - Article
AN - SCOPUS:84865760150
SN - 0018-9529
VL - 61
SP - 675
EP - 686
JO - IEEE Transactions on Reliability
JF - IEEE Transactions on Reliability
IS - 3
M1 - 6239638
ER -