Path-delay fault simulation for circuits with large numbers of paths for very large test sets

N. M. Abdulrazzaq, S. K. Gupta

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

We propose an exact non-enumerative path-delay fault simulation technique for combinational circuits using very large test sets. We focus on combinational circuits that contain very large numbers of path delay faults, for example, c6288 that has about 2×1020 possible path-delay faults. Enumerative fault simulators simply cannot handle such circuits. Existing non-enumerative fault simulators work for small test sets only. The proposed method uses the mathematical principle of inclusion and exclusion and handles the large number of tests using a novel encoding technique.

Original languageEnglish
Title of host publicationProceedings - 21st IEEE VLSI Test Symposium, VTS 2003
PublisherIEEE Computer Society
Pages186-193
Number of pages8
ISBN (Electronic)0769519245
DOIs
Publication statusPublished - 2003
Event21st IEEE VLSI Test Symposium, VTS 2003 - Napa Valley, United States
Duration: Apr 27 2003May 1 2003

Publication series

NameProceedings of the IEEE VLSI Test Symposium
Volume2003-January

Other

Other21st IEEE VLSI Test Symposium, VTS 2003
Country/TerritoryUnited States
CityNapa Valley
Period4/27/035/1/03

Keywords

  • Algebra
  • Circuit faults
  • Circuit simulation
  • Circuit testing
  • Combinational circuits
  • Computational modeling
  • Delay
  • Electrical fault detection
  • Encoding
  • Fault detection

ASJC Scopus subject areas

  • Computer Science Applications
  • Electrical and Electronic Engineering

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