@inproceedings{d1e32fc215d44dcabc3767c78c6b0c2e,
title = "Path-delay fault simulation for circuits with large numbers of paths for very large test sets",
abstract = "We propose an exact non-enumerative path-delay fault simulation technique for combinational circuits using very large test sets. We focus on combinational circuits that contain very large numbers of path delay faults, for example, c6288 that has about 2×1020 possible path-delay faults. Enumerative fault simulators simply cannot handle such circuits. Existing non-enumerative fault simulators work for small test sets only. The proposed method uses the mathematical principle of inclusion and exclusion and handles the large number of tests using a novel encoding technique.",
keywords = "Algebra, Circuit faults, Circuit simulation, Circuit testing, Combinational circuits, Computational modeling, Delay, Electrical fault detection, Encoding, Fault detection",
author = "Abdulrazzaq, {N. M.} and Gupta, {S. K.}",
year = "2003",
month = jan,
day = "1",
doi = "10.1109/VTEST.2003.1197650",
language = "English",
series = "Proceedings of the IEEE VLSI Test Symposium",
publisher = "IEEE Computer Society",
pages = "186--193",
booktitle = "Proceedings - 21st IEEE VLSI Test Symposium, VTS 2003",
note = "21st IEEE VLSI Test Symposium, VTS 2003 ; Conference date: 27-04-2003 Through 01-05-2003",
}