Performance analysis of Viterbi decoder using a DSP technique

S. K. Hasnain, Azam Beg, S. M.Ghazanfar Monir

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

Increasing the speed of the wireless communication requires a reliable solution for data transfer. The signal to noise ratio (SNR) of the channel in digital wireless communication is one of the major limitations on the operating performance. To enhance the performance, solution in terms of coded data and error-correcting code has been introduced. Viterbi decoder is one of the techniques used for this purpose and Viterbi algorithm is used for decoding. This algorithm is an extremely fast and efficient method of decoding the coded data from the channel. In this paper, the structure of baseband processing unit and implementation of convolutional encoder and Viterbi decoder is described. The convolutional encoder of rate 1/2 and constraint length 3 and Viterbi decoder of rate 1/2 and constraint length 3 using a TMS320C54 DSP chip is designed.

Original languageEnglish
Title of host publicationProceedings of INMIC 2004 - 8th International Multitopic Conference
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages201-207
Number of pages7
ISBN (Electronic)0780386809, 9780780386808
DOIs
Publication statusPublished - Jan 1 2004
Externally publishedYes
Event8th International Multitopic Conference, INMIC 2004 - Lahore, Pakistan
Duration: Dec 24 2004Dec 26 2004

Publication series

NameProceedings of INMIC 2004 - 8th International Multitopic Conference

Other

Other8th International Multitopic Conference, INMIC 2004
Country/TerritoryPakistan
CityLahore
Period12/24/0412/26/04

ASJC Scopus subject areas

  • Engineering(all)
  • Computer Science(all)

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