Performance limits for processor networks with divisible jobs

Sameer Bataineh; Thomas G. Robertazzi

doi:10.1109/7.625112

Performance limits for processor networks with divisible jobs

Sameer Bataineh, Thomas G. Robertazzi

Research output: Contribution to journal › Article › peer-review

10 Citations (Scopus)

Abstract

Ultimate performance limits to the aggregate processing speed of networks of processors that are processing a divisible job are described. These take the form of either closed-form expressions or numerical procedures to calculate the equivalent processing speed of an infinite number of processors. These processors are interconnected in either a linear daisy chain with load origination from the network interior or a tree topology. The tree topology is particularly general as a natural way to perform load distribution in a processor network topology with cycles (e.g., hypercube, toroidal network) is to use an embedded spanning tree. Such limits on performance are important as they provide an ideal baseline against which to compare the performance of finite configurations of processors.

Original language	English
Pages (from-to)	1189-1198
Number of pages	10
Journal	IEEE Transactions on Aerospace and Electronic Systems
Volume	33
Issue number	4
DOIs	https://doi.org/10.1109/7.625112
Publication status	Published - 1997
Externally published	Yes

ASJC Scopus subject areas

Aerospace Engineering
Electrical and Electronic Engineering

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10.1109/7.625112

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@article{47474a0ebf4d49b9944146d3841bb5aa,

title = "Performance limits for processor networks with divisible jobs",

abstract = "Ultimate performance limits to the aggregate processing speed of networks of processors that are processing a divisible job are described. These take the form of either closed-form expressions or numerical procedures to calculate the equivalent processing speed of an infinite number of processors. These processors are interconnected in either a linear daisy chain with load origination from the network interior or a tree topology. The tree topology is particularly general as a natural way to perform load distribution in a processor network topology with cycles (e.g., hypercube, toroidal network) is to use an embedded spanning tree. Such limits on performance are important as they provide an ideal baseline against which to compare the performance of finite configurations of processors.",

author = "Sameer Bataineh and Robertazzi, {Thomas G.}",

note = "Funding Information: This work is supported by the BMDO/IST under the Office of the Naval Research under Grant N00014-91-J4063.",

year = "1997",

doi = "10.1109/7.625112",

language = "English",

volume = "33",

pages = "1189--1198",

journal = "IEEE Transactions on Aerospace and Electronic Systems",

issn = "0018-9251",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "4",

}

TY - JOUR

T1 - Performance limits for processor networks with divisible jobs

AU - Bataineh, Sameer

AU - Robertazzi, Thomas G.

N1 - Funding Information: This work is supported by the BMDO/IST under the Office of the Naval Research under Grant N00014-91-J4063.

PY - 1997

Y1 - 1997

N2 - Ultimate performance limits to the aggregate processing speed of networks of processors that are processing a divisible job are described. These take the form of either closed-form expressions or numerical procedures to calculate the equivalent processing speed of an infinite number of processors. These processors are interconnected in either a linear daisy chain with load origination from the network interior or a tree topology. The tree topology is particularly general as a natural way to perform load distribution in a processor network topology with cycles (e.g., hypercube, toroidal network) is to use an embedded spanning tree. Such limits on performance are important as they provide an ideal baseline against which to compare the performance of finite configurations of processors.

AB - Ultimate performance limits to the aggregate processing speed of networks of processors that are processing a divisible job are described. These take the form of either closed-form expressions or numerical procedures to calculate the equivalent processing speed of an infinite number of processors. These processors are interconnected in either a linear daisy chain with load origination from the network interior or a tree topology. The tree topology is particularly general as a natural way to perform load distribution in a processor network topology with cycles (e.g., hypercube, toroidal network) is to use an embedded spanning tree. Such limits on performance are important as they provide an ideal baseline against which to compare the performance of finite configurations of processors.

UR - http://www.scopus.com/inward/record.url?scp=0031257525&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0031257525&partnerID=8YFLogxK

U2 - 10.1109/7.625112

DO - 10.1109/7.625112

M3 - Article

AN - SCOPUS:0031257525

SN - 0018-9251

VL - 33

SP - 1189

EP - 1198

JO - IEEE Transactions on Aerospace and Electronic Systems

JF - IEEE Transactions on Aerospace and Electronic Systems

IS - 4

ER -

Performance limits for processor networks with divisible jobs

Abstract

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