Predicting processor performance with a machine learnt model

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    9 Citations (Scopus)

    Abstract

    Architectural simulators are traditionally used to study the design trade-offs for processor systems. The simulators are implemented in a high-level programming language or a hardware descriptive language, and are used to estimate the system performance prior to the hardware implementation. The simulations, however, may need to run for long periods of time for even a small set of design variations. In this paper, we propose a machine learnt (neural network/NN) model for estimating the execution performance of a superscalar processor. Multiple runs for the model are finished in less than a few milliseconds as compared to days or weeks required for simulation-based methods. The model is able to predict the execution throughput of a processor system with over 85% accuracy when tested with six SPEC2000 CPU integer benchmarks. The proposed model has possible applications in computer architecture research and teaching.

    Original languageEnglish
    Title of host publication2007 50th Midwest Symposium on Circuits and Systems, MWSCAS - Conference Proceedings
    Pages1098-1101
    Number of pages4
    DOIs
    Publication statusPublished - 2007
    Event2007 50th Midwest Symposium on Circuits and Systems, MWSCAS - Conference - Montreal, QC, Canada
    Duration: Aug 5 2007Aug 8 2007

    Publication series

    NameMidwest Symposium on Circuits and Systems
    ISSN (Print)1548-3746

    Other

    Other2007 50th Midwest Symposium on Circuits and Systems, MWSCAS - Conference
    Country/TerritoryCanada
    CityMontreal, QC
    Period8/5/078/8/07

    ASJC Scopus subject areas

    • Electronic, Optical and Magnetic Materials
    • Electrical and Electronic Engineering

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