TY - GEN
T1 - Predicting processor performance with a machine learnt model
AU - Beg, Azam
PY - 2007
Y1 - 2007
N2 - Architectural simulators are traditionally used to study the design trade-offs for processor systems. The simulators are implemented in a high-level programming language or a hardware descriptive language, and are used to estimate the system performance prior to the hardware implementation. The simulations, however, may need to run for long periods of time for even a small set of design variations. In this paper, we propose a machine learnt (neural network/NN) model for estimating the execution performance of a superscalar processor. Multiple runs for the model are finished in less than a few milliseconds as compared to days or weeks required for simulation-based methods. The model is able to predict the execution throughput of a processor system with over 85% accuracy when tested with six SPEC2000 CPU integer benchmarks. The proposed model has possible applications in computer architecture research and teaching.
AB - Architectural simulators are traditionally used to study the design trade-offs for processor systems. The simulators are implemented in a high-level programming language or a hardware descriptive language, and are used to estimate the system performance prior to the hardware implementation. The simulations, however, may need to run for long periods of time for even a small set of design variations. In this paper, we propose a machine learnt (neural network/NN) model for estimating the execution performance of a superscalar processor. Multiple runs for the model are finished in less than a few milliseconds as compared to days or weeks required for simulation-based methods. The model is able to predict the execution throughput of a processor system with over 85% accuracy when tested with six SPEC2000 CPU integer benchmarks. The proposed model has possible applications in computer architecture research and teaching.
UR - http://www.scopus.com/inward/record.url?scp=51449119412&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=51449119412&partnerID=8YFLogxK
U2 - 10.1109/MWSCAS.2007.4488749
DO - 10.1109/MWSCAS.2007.4488749
M3 - Conference contribution
AN - SCOPUS:51449119412
SN - 1424411769
SN - 9781424411764
T3 - Midwest Symposium on Circuits and Systems
SP - 1098
EP - 1101
BT - 2007 50th Midwest Symposium on Circuits and Systems, MWSCAS - Conference Proceedings
T2 - 2007 50th Midwest Symposium on Circuits and Systems, MWSCAS - Conference
Y2 - 5 August 2007 through 8 August 2007
ER -