On-Chip Inductance has become of significance in the design of high-speed interconnects. In this paper, three techniques are applied to regenerate an RLC interconnect in series, parallel and without regeneration. Simulations using a 0.25 μm TSMC technology show that the parallel regeneration starts achieving a better speed than the non-regenerated line at wire lengths smaller than that achieved when the wire is serially regenerated. It also features 47% time delay saving and 96% Area-Delay product saving over the serial regeneration.
|Title of host publication
|ICM 2001 Proceedings - 13th International Conference on Microelectronics
|Institute of Electrical and Electronics Engineers Inc.
|Number of pages
|Published - Jan 1 2001
|13th International Conference on Microelectronics, ICM 2001 - Rabat, Morocco
Duration: Oct 29 2001 → Oct 31 2001
|Proceedings of the International Conference on Microelectronics, ICM
|13th International Conference on Microelectronics, ICM 2001
|10/29/01 → 10/31/01
ASJC Scopus subject areas
- Electrical and Electronic Engineering