TY - GEN
T1 - Regeneration techniques for RLC VLSI interconnects
AU - Awwad, Falah R.
AU - Nekili, Mohamed
PY - 2001/1/1
Y1 - 2001/1/1
N2 - On-Chip Inductance has become of significance in the design of high-speed interconnects. In this paper, three techniques are applied to regenerate an RLC interconnect in series, parallel and without regeneration. Simulations using a 0.25 μm TSMC technology show that the parallel regeneration starts achieving a better speed than the non-regenerated line at wire lengths smaller than that achieved when the wire is serially regenerated. It also features 47% time delay saving and 96% Area-Delay product saving over the serial regeneration.
AB - On-Chip Inductance has become of significance in the design of high-speed interconnects. In this paper, three techniques are applied to regenerate an RLC interconnect in series, parallel and without regeneration. Simulations using a 0.25 μm TSMC technology show that the parallel regeneration starts achieving a better speed than the non-regenerated line at wire lengths smaller than that achieved when the wire is serially regenerated. It also features 47% time delay saving and 96% Area-Delay product saving over the serial regeneration.
UR - http://www.scopus.com/inward/record.url?scp=42949165047&partnerID=8YFLogxK
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U2 - 10.1109/ICM.2001.997647
DO - 10.1109/ICM.2001.997647
M3 - Conference contribution
AN - SCOPUS:42949165047
T3 - Proceedings of the International Conference on Microelectronics, ICM
SP - 209
EP - 212
BT - ICM 2001 Proceedings - 13th International Conference on Microelectronics
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 13th International Conference on Microelectronics, ICM 2001
Y2 - 29 October 2001 through 31 October 2001
ER -