Regeneration techniques for RLC VLSI interconnects

Falah R. Awwad, Mohamed Nekili

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)


On-Chip Inductance has become of significance in the design of high-speed interconnects. In this paper, three techniques are applied to regenerate an RLC interconnect in series, parallel and without regeneration. Simulations using a 0.25 μm TSMC technology show that the parallel regeneration starts achieving a better speed than the non-regenerated line at wire lengths smaller than that achieved when the wire is serially regenerated. It also features 47% time delay saving and 96% Area-Delay product saving over the serial regeneration.

Original languageEnglish
Title of host publicationICM 2001 Proceedings - 13th International Conference on Microelectronics
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages4
ISBN (Electronic)078037522X
Publication statusPublished - 2001
Externally publishedYes
Event13th International Conference on Microelectronics, ICM 2001 - Rabat, Morocco
Duration: Oct 29 2001Oct 31 2001

Publication series

NameProceedings of the International Conference on Microelectronics, ICM


Other13th International Conference on Microelectronics, ICM 2001

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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