Relating reliability to circuit topology

Azam Beg; Walid Ibrahim

doi:10.1109/NEWCAS.2009.5290421

Relating reliability to circuit topology

Azam Beg, Walid Ibrahim

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

10 Citations (Scopus)

Abstract

Reliability analysis of nano-scale circuits can be done using different techniques, one of them being Bayesian networks. Using this scheme, the relationship of circuit's topology to reliability has been studied for several thousand randomly generated (combinational) 3 to 9 variable circuits; the circuits contained up to 40 gates in up to 10 tiers/levels. As anticipated, strong, positive correlations were found between gate counts and circuit's probability of failure (PF), and between the level counts and circuit PF. However, the input counts and the circuit PFs were weakly correlated. These findings can be useful in creating reliability models for arbitrary circuits.

Original language	English
Title of host publication	2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09
DOIs	https://doi.org/10.1109/NEWCAS.2009.5290421
Publication status	Published - Dec 24 2009
Event	2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09 - Toulouse, France Duration: Jun 28 2009 → Jul 1 2009

Publication series

Name	2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09

Other

Other	2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09
Country/Territory	France
City	Toulouse
Period	6/28/09 → 7/1/09

ASJC Scopus subject areas

Hardware and Architecture
Control and Systems Engineering
Electrical and Electronic Engineering

Access to Document

10.1109/NEWCAS.2009.5290421

Cite this

Relating reliability to circuit topology. / Beg, Azam ; Ibrahim, Walid.
2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09. 2009. 5290421 (2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Beg, A & Ibrahim, W 2009, Relating reliability to circuit topology. in 2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09., 5290421, 2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09, 2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09, Toulouse, France, 6/28/09. https://doi.org/10.1109/NEWCAS.2009.5290421

@inproceedings{9b987b7cce8646b684d5a65c68ba4e9b,

title = "Relating reliability to circuit topology",

abstract = "Reliability analysis of nano-scale circuits can be done using different techniques, one of them being Bayesian networks. Using this scheme, the relationship of circuit's topology to reliability has been studied for several thousand randomly generated (combinational) 3 to 9 variable circuits; the circuits contained up to 40 gates in up to 10 tiers/levels. As anticipated, strong, positive correlations were found between gate counts and circuit's probability of failure (PF), and between the level counts and circuit PF. However, the input counts and the circuit PFs were weakly correlated. These findings can be useful in creating reliability models for arbitrary circuits.",

author = "Azam Beg and Walid Ibrahim",

year = "2009",

month = dec,

day = "24",

doi = "10.1109/NEWCAS.2009.5290421",

language = "English",

isbn = "9781424445738",

series = "2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09",

booktitle = "2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09",

note = "2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09 ; Conference date: 28-06-2009 Through 01-07-2009",

}

TY - GEN

T1 - Relating reliability to circuit topology

AU - Beg, Azam

AU - Ibrahim, Walid

PY - 2009/12/24

Y1 - 2009/12/24

N2 - Reliability analysis of nano-scale circuits can be done using different techniques, one of them being Bayesian networks. Using this scheme, the relationship of circuit's topology to reliability has been studied for several thousand randomly generated (combinational) 3 to 9 variable circuits; the circuits contained up to 40 gates in up to 10 tiers/levels. As anticipated, strong, positive correlations were found between gate counts and circuit's probability of failure (PF), and between the level counts and circuit PF. However, the input counts and the circuit PFs were weakly correlated. These findings can be useful in creating reliability models for arbitrary circuits.

AB - Reliability analysis of nano-scale circuits can be done using different techniques, one of them being Bayesian networks. Using this scheme, the relationship of circuit's topology to reliability has been studied for several thousand randomly generated (combinational) 3 to 9 variable circuits; the circuits contained up to 40 gates in up to 10 tiers/levels. As anticipated, strong, positive correlations were found between gate counts and circuit's probability of failure (PF), and between the level counts and circuit PF. However, the input counts and the circuit PFs were weakly correlated. These findings can be useful in creating reliability models for arbitrary circuits.

UR - http://www.scopus.com/inward/record.url?scp=72249108767&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=72249108767&partnerID=8YFLogxK

U2 - 10.1109/NEWCAS.2009.5290421

DO - 10.1109/NEWCAS.2009.5290421

M3 - Conference contribution

AN - SCOPUS:72249108767

SN - 9781424445738

T3 - 2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09

BT - 2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09

T2 - 2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09

Y2 - 28 June 2009 through 1 July 2009

ER -

Relating reliability to circuit topology

Abstract

Publication series

Other

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this