Relating reliability to circuit topology

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    9 Citations (Scopus)

    Abstract

    Reliability analysis of nano-scale circuits can be done using different techniques, one of them being Bayesian networks. Using this scheme, the relationship of circuit's topology to reliability has been studied for several thousand randomly generated (combinational) 3 to 9 variable circuits; the circuits contained up to 40 gates in up to 10 tiers/levels. As anticipated, strong, positive correlations were found between gate counts and circuit's probability of failure (PF), and between the level counts and circuit PF. However, the input counts and the circuit PFs were weakly correlated. These findings can be useful in creating reliability models for arbitrary circuits.

    Original languageEnglish
    Title of host publication2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09
    DOIs
    Publication statusPublished - Dec 24 2009
    Event2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09 - Toulouse, France
    Duration: Jun 28 2009Jul 1 2009

    Publication series

    Name2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09

    Other

    Other2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09
    Country/TerritoryFrance
    CityToulouse
    Period6/28/097/1/09

    ASJC Scopus subject areas

    • Hardware and Architecture
    • Control and Systems Engineering
    • Electrical and Electronic Engineering

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