Reliability enhanced SRAM bit-cells

Valeriu Beiu; Mihai Tache; Fekri Kharbash

doi:10.1109/SMICND.2014.6966444

Reliability enhanced SRAM bit-cells

Valeriu Beiu, Mihai Tache, Fekri Kharbash

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Noises and variations are ubiquitous, but are ill-understood and in most cases analyzed simplistically, leading to substantial overdesign costs. A novel reliability-centric design method based on unconventionally sizing transistors has been suggested lately. In this paper our aim is to design, simulate, and compare the benefits of unconventional sizing when applied to SRAM bit-cells. The unconventionally sized SRAM bit-cells achieve higher SNMs, having the potential to work correctly at supply voltages lower than those achieved using classically sized SRAM bit-cells.

Original language	English
Title of host publication	Proceedings of the International Semiconductor Conference, CAS
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	229-232
Number of pages	4
ISBN (Electronic)	9781479939169
DOIs	https://doi.org/10.1109/SMICND.2014.6966444
Publication status	Published - Nov 24 2014
Event	37th International Semiconductor Conference, CAS 2014 - Sinaia, Romania Duration: Oct 13 2014 → Oct 15 2014

Publication series

Name	Proceedings of the International Semiconductor Conference, CAS

Conference

Conference	37th International Semiconductor Conference, CAS 2014
Country/Territory	Romania
City	Sinaia
Period	10/13/14 → 10/15/14

Keywords

CMOS
SNM
SRAM
reliability
sizing

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering

Access to Document

10.1109/SMICND.2014.6966444

Cite this

Reliability enhanced SRAM bit-cells. / Beiu, Valeriu; Tache, Mihai; Kharbash, Fekri.
Proceedings of the International Semiconductor Conference, CAS. Institute of Electrical and Electronics Engineers Inc., 2014. p. 229-232 6966444 (Proceedings of the International Semiconductor Conference, CAS).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Beiu, V, Tache, M & Kharbash, F 2014, Reliability enhanced SRAM bit-cells. in Proceedings of the International Semiconductor Conference, CAS., 6966444, Proceedings of the International Semiconductor Conference, CAS, Institute of Electrical and Electronics Engineers Inc., pp. 229-232, 37th International Semiconductor Conference, CAS 2014, Sinaia, Romania, 10/13/14. https://doi.org/10.1109/SMICND.2014.6966444

@inproceedings{fa96a3b317fe42c48d87f0a87e860302,

title = "Reliability enhanced SRAM bit-cells",

abstract = "Noises and variations are ubiquitous, but are ill-understood and in most cases analyzed simplistically, leading to substantial overdesign costs. A novel reliability-centric design method based on unconventionally sizing transistors has been suggested lately. In this paper our aim is to design, simulate, and compare the benefits of unconventional sizing when applied to SRAM bit-cells. The unconventionally sized SRAM bit-cells achieve higher SNMs, having the potential to work correctly at supply voltages lower than those achieved using classically sized SRAM bit-cells.",

keywords = "CMOS, SNM, SRAM, reliability, sizing",

author = "Valeriu Beiu and Mihai Tache and Fekri Kharbash",

note = "Publisher Copyright: {\textcopyright} 2014 IEEE.; 37th International Semiconductor Conference, CAS 2014 ; Conference date: 13-10-2014 Through 15-10-2014",

year = "2014",

month = nov,

day = "24",

doi = "10.1109/SMICND.2014.6966444",

language = "English",

series = "Proceedings of the International Semiconductor Conference, CAS",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "229--232",

booktitle = "Proceedings of the International Semiconductor Conference, CAS",

}

TY - GEN

T1 - Reliability enhanced SRAM bit-cells

AU - Beiu, Valeriu

AU - Tache, Mihai

AU - Kharbash, Fekri

PY - 2014/11/24

Y1 - 2014/11/24

N2 - Noises and variations are ubiquitous, but are ill-understood and in most cases analyzed simplistically, leading to substantial overdesign costs. A novel reliability-centric design method based on unconventionally sizing transistors has been suggested lately. In this paper our aim is to design, simulate, and compare the benefits of unconventional sizing when applied to SRAM bit-cells. The unconventionally sized SRAM bit-cells achieve higher SNMs, having the potential to work correctly at supply voltages lower than those achieved using classically sized SRAM bit-cells.

AB - Noises and variations are ubiquitous, but are ill-understood and in most cases analyzed simplistically, leading to substantial overdesign costs. A novel reliability-centric design method based on unconventionally sizing transistors has been suggested lately. In this paper our aim is to design, simulate, and compare the benefits of unconventional sizing when applied to SRAM bit-cells. The unconventionally sized SRAM bit-cells achieve higher SNMs, having the potential to work correctly at supply voltages lower than those achieved using classically sized SRAM bit-cells.

KW - CMOS

KW - SNM

KW - SRAM

KW - reliability

KW - sizing

UR - http://www.scopus.com/inward/record.url?scp=84916608309&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84916608309&partnerID=8YFLogxK

U2 - 10.1109/SMICND.2014.6966444

DO - 10.1109/SMICND.2014.6966444

M3 - Conference contribution

AN - SCOPUS:84916608309

T3 - Proceedings of the International Semiconductor Conference, CAS

SP - 229

EP - 232

BT - Proceedings of the International Semiconductor Conference, CAS

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 37th International Semiconductor Conference, CAS 2014

Y2 - 13 October 2014 through 15 October 2014

ER -

Reliability enhanced SRAM bit-cells

Abstract

Publication series

Conference

Keywords

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this