Reliability enhanced SRAM bit-cells

Valeriu Beiu, Mihai Tache, Fekri Kharbash

    Research output: Chapter in Book/Report/Conference proceedingConference contribution


    Noises and variations are ubiquitous, but are ill-understood and in most cases analyzed simplistically, leading to substantial overdesign costs. A novel reliability-centric design method based on unconventionally sizing transistors has been suggested lately. In this paper our aim is to design, simulate, and compare the benefits of unconventional sizing when applied to SRAM bit-cells. The unconventionally sized SRAM bit-cells achieve higher SNMs, having the potential to work correctly at supply voltages lower than those achieved using classically sized SRAM bit-cells.

    Original languageEnglish
    Title of host publicationProceedings of the International Semiconductor Conference, CAS
    PublisherInstitute of Electrical and Electronics Engineers Inc.
    Number of pages4
    ISBN (Electronic)9781479939169
    Publication statusPublished - Nov 24 2014
    Event37th International Semiconductor Conference, CAS 2014 - Sinaia, Romania
    Duration: Oct 13 2014Oct 15 2014

    Publication series

    NameProceedings of the International Semiconductor Conference, CAS


    Conference37th International Semiconductor Conference, CAS 2014


    • CMOS
    • SNM
    • SRAM
    • reliability
    • sizing

    ASJC Scopus subject areas

    • Electronic, Optical and Magnetic Materials
    • Condensed Matter Physics
    • Electrical and Electronic Engineering


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