Reliability modeling and optimization of CMOS standard cells

Azam Beg, Rashad Ramzan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

This paper presents a mathematical model-based method for calculating the reliability of nanometric CMOS standard logic cells. The models are useful in quickly identifying the supply voltages and MOS transistor sizes that would result in low unreliability while lowering the power and/or delay. By using the example of a medium-complexity cell, i.e., a full adder, we show how the reliability, power and delay can be considered simultaneously to achieve an optimal cell design. The presented method is scalable and is readily usable for other types of logic cells.

Original languageEnglish
Title of host publicationWMSCI 2019 - 23rd World Multi-Conference on Systemics, Cybernetics and Informatics, Proceedings
EditorsNagib C. Callaos, Bruce E. Peoples, Belkis Sanchez, Michael Savoie
PublisherInternational Institute of Informatics and Systemics, IIIS
Pages82-85
Number of pages4
ISBN (Electronic)9781950492084
Publication statusPublished - 2019
Event23rd World Multi-Conference on Systemics, Cybernetics and Informatics, WMSCI 2019 - Orlando, United States
Duration: Jul 6 2019Jul 9 2019

Publication series

NameWMSCI 2019 - 23rd World Multi-Conference on Systemics, Cybernetics and Informatics, Proceedings
Volume1

Conference

Conference23rd World Multi-Conference on Systemics, Cybernetics and Informatics, WMSCI 2019
Country/TerritoryUnited States
CityOrlando
Period7/6/197/9/19

Keywords

  • CMOS standard cell
  • Delay
  • Full adder
  • Mathematical model
  • Optimization
  • Performance
  • Power
  • Reliability

ASJC Scopus subject areas

  • Artificial Intelligence
  • Computer Networks and Communications
  • Information Systems

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