Reliable binary signed digit number adder design

F. Kharbash; G. M. Chaudhry

doi:10.1109/ISVLSI.2007.88

Reliable binary signed digit number adder design

F. Kharbash, G. M. Chaudhry

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

5 Citations (Scopus)

Abstract

The Binary Signed Digit Number (BSDN) system is used implicitly or explicitly to speed up arithmetic operations in many digital systems. This is due to its capability of carry-free addition and regular layout. Also, with the proper selection of the encoding scheme used to encode the BSDN digit set D={-1, 0, 1} into binary bits, an error detection capability feature can be gained. In this work, we present the design of BSDN full adder cell using the 1-out-of-3 encoding with and without error detection capability. Synthesis results showed that the carry-free addition feature of the BSDN adder is preserved in the proposed design regardless of the inputs size. Also the overall adder performance depends on the desired level of error detection and the effectiveness of the used BSDN full adder.

Original language	English
Title of host publication	Proceedings - IEEE Computer Society Annual Symposium on VLSI
Subtitle of host publication	Emerging VLSI Technologies and Architectures
Pages	479-484
Number of pages	6
DOIs	https://doi.org/10.1109/ISVLSI.2007.88
Publication status	Published - 2007
Externally published	Yes
Event	IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures, ISVLSI'07 - Porto Alegre, Brazil Duration: Mar 9 2007 → Mar 11 2007

Publication series

Name	Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures

Other

Other	IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures, ISVLSI'07
Country/Territory	Brazil
City	Porto Alegre
Period	3/9/07 → 3/11/07

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/ISVLSI.2007.88

Cite this

Kharbash, F., & Chaudhry, G. M. (2007). Reliable binary signed digit number adder design. In Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures (pp. 479-484). Article 4208966 (Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures). https://doi.org/10.1109/ISVLSI.2007.88

Reliable binary signed digit number adder design. / Kharbash, F.; Chaudhry, G. M.
Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures. 2007. p. 479-484 4208966 (Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Kharbash, F & Chaudhry, GM 2007, Reliable binary signed digit number adder design. in Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures., 4208966, Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures, pp. 479-484, IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures, ISVLSI'07, Porto Alegre, Brazil, 3/9/07. https://doi.org/10.1109/ISVLSI.2007.88

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Reliable binary signed digit number adder design

Abstract

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