@inproceedings{da555a2a0f3c4ea1a8dad147a759bad0,
title = "Review of differential threshold gate implementations",
abstract = "The different implementations of threshold logic gates (TLG) detailing capacitive (floating gate and switched capacitor) and conductance/current were discussed. It is found that the Differential Current-Switch Threshold Logic (DCSTL) restricted the voltage swing of the internal nodes for lowering the power consumption. The Current-Mode Threshold Logic (CMTL) which used two banks of parallel transistor for inputs and threshold was studied. Analysis shows that the power reduction come both from having fewer TLGs and from using the new Split-Precharge Differential Noise-Immune Threshold Logic (SPD-NTL) gates.",
keywords = "Differential gates, Neural network, Perceptron, Threshold logic, VLSI",
author = "V. Beiu and Quintana, {J. M.} and Avedilo, {M. J.}",
year = "2003",
language = "English",
isbn = "0889863474",
series = "Proceedings of the IASTED International Conference on Neural Networks and Computational Intelligence",
pages = "44--49",
editor = "O. Coastillo",
booktitle = "Proceedings of the IASTED International Conference on Neural Networks and Computational Intelligence",
note = "Proceedings of the IASTED International Conference on Neural Networks and Computational Intelligence ; Conference date: 19-05-2003 Through 21-05-2003",
}