Review of Recent Full Adders Implemented in Single Electron Technology

Mawahib H. Sulieman, Valeriu Beiu

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)


    This paper reviews several full adder designs in single electron technology (SET). Different SET designs of full adders were introduced recently. In addition to the structure and size reported for these full adders, this paper also provides a quantitative comparison in terms of delay and power dissipation. This allows for a better understanding of the advantages and disadvantages of each solution. In addition, an improved FA design based on capacitive threshold logic gates are presented.
    Original languageEnglish
    Title of host publicationIEEE International Midwest Symposium on Circuit and Systems
    Publication statusPublished - Dec 27 2003
    EventMWSCAS'03 - Cairo, Egypt
    Duration: Dec 27 2003 → …


    Period12/27/03 → …


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