Review of Recent Full Adders Implemented in Single Electron Technology

Mawahib H. Sulieman; Valeriu Beiu

doi:10.1109/MWSCAS.2003.1562425

Review of Recent Full Adders Implemented in Single Electron Technology

Mawahib H. Sulieman, Valeriu Beiu

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper reviews several full adder designs in single electron technology (SET). Different SET designs of full adders were introduced recently. In addition to the structure and size reported for these full adders, this paper also provides a quantitative comparison in terms of delay and power dissipation. This allows for a better understanding of the advantages and disadvantages of each solution. In addition, an improved FA design based on capacitive threshold logic gates are presented.

Original language	English
Title of host publication	IEEE International Midwest Symposium on Circuit and Systems
DOIs	https://doi.org/10.1109/MWSCAS.2003.1562425
Publication status	Published - Dec 27 2003
Event	MWSCAS'03 - Cairo, Egypt Duration: Dec 27 2003 → …

Conference

Conference	MWSCAS'03
Period	12/27/03 → …

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10.1109/MWSCAS.2003.1562425

http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=1562425&url=http%3A%2F%2Fieeexplore.ieee.org%2Fxpls%2Fabs_all.jsp%3Farnumber%3D1562425

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@inproceedings{19a8217c8cfc4424b93c4de315d86357,

title = "Review of Recent Full Adders Implemented in Single Electron Technology",

abstract = "This paper reviews several full adder designs in single electron technology (SET). Different SET designs of full adders were introduced recently. In addition to the structure and size reported for these full adders, this paper also provides a quantitative comparison in terms of delay and power dissipation. This allows for a better understanding of the advantages and disadvantages of each solution. In addition, an improved FA design based on capacitive threshold logic gates are presented.",

author = "Sulieman, {Mawahib H.} and Valeriu Beiu",

year = "2003",

month = dec,

day = "27",

doi = "10.1109/MWSCAS.2003.1562425",

language = "English",

booktitle = "IEEE International Midwest Symposium on Circuit and Systems",

note = "MWSCAS'03 ; Conference date: 27-12-2003",

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AB - This paper reviews several full adder designs in single electron technology (SET). Different SET designs of full adders were introduced recently. In addition to the structure and size reported for these full adders, this paper also provides a quantitative comparison in terms of delay and power dissipation. This allows for a better understanding of the advantages and disadvantages of each solution. In addition, an improved FA design based on capacitive threshold logic gates are presented.

U2 - 10.1109/MWSCAS.2003.1562425

DO - 10.1109/MWSCAS.2003.1562425

M3 - Conference contribution

BT - IEEE International Midwest Symposium on Circuit and Systems

T2 - MWSCAS'03

Y2 - 27 December 2003

ER -

Review of Recent Full Adders Implemented in Single Electron Technology

Abstract

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