TY - JOUR
T1 - Room temperature logic inverter on epitaxial graphene-on-silicon device
AU - El Moutaouakil, Amine
AU - Kang, Hyun Chul
AU - Handa, Hiroyuki
AU - Fukidome, Hirokazu
AU - Suemitsu, Tetsuya
AU - Sano, Eiichi
AU - Suemitsu, Maki
AU - Otsuji, Taiichi
PY - 2011/7
Y1 - 2011/7
N2 - The inverting operation of a logic inverter, using two back-gate epitaxial graphene-on-silicon field-effect transistors (GOSFETs), is demonstrated at room temperature. Thanks to the asymmetric ambipolarity of the fabricated GOSFETs, owing to the undesirable back-gate leakage, the on/off state current has been dramatically reduced. This results in a well matched input/output voltage levels for a wide VDD range from more than 1 V down to 0.5 V. The inverting operation of the device is obtained at as low VDD bias as 0.5 V. Voltage gains higher than the unity are also obtained. The experimental results are in good agreement with the simulation results made for the case of asymmetric ambipolar transistors.
AB - The inverting operation of a logic inverter, using two back-gate epitaxial graphene-on-silicon field-effect transistors (GOSFETs), is demonstrated at room temperature. Thanks to the asymmetric ambipolarity of the fabricated GOSFETs, owing to the undesirable back-gate leakage, the on/off state current has been dramatically reduced. This results in a well matched input/output voltage levels for a wide VDD range from more than 1 V down to 0.5 V. The inverting operation of the device is obtained at as low VDD bias as 0.5 V. Voltage gains higher than the unity are also obtained. The experimental results are in good agreement with the simulation results made for the case of asymmetric ambipolar transistors.
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U2 - 10.1143/JJAP.50.070113
DO - 10.1143/JJAP.50.070113
M3 - Article
AN - SCOPUS:79960687438
SN - 0021-4922
VL - 50
JO - Japanese Journal of Applied Physics
JF - Japanese Journal of Applied Physics
IS - 7 PART 1
M1 - 070113
ER -