TY - GEN
T1 - Sensitivity of reliability of logic gates
AU - Beg, Azam
AU - Jaffri, Ifrah
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2017/6/28
Y1 - 2017/6/28
N2 - Ever-shrinking dimensions of transistors in CMOS have caused the failure rates/probabilities to increase dramatically. Monte Carlo simulations are one way of estimation the failure probabilities, however, such simulations tend to be very time-consuming. A much speedier alternative is to use models for the estimation. This paper presents a method for creating the mathematical models for the probabilities of failures of CMOS logic gates/blocks. The models of five common gates are included, i.e., NAND3, NAND4, NOR3, NOR4 and OAI22. The models can also be used to study the sensitivity of the gates' failures to their individual transistors' failures. The presented technique is applicable to larger logic cells such as 28-transistor full-adders, etc. The given models are anticipated to be useful for Pareto-optimization of logic blocks, for instance, power-and-reliability, performance-and-reliability etc.
AB - Ever-shrinking dimensions of transistors in CMOS have caused the failure rates/probabilities to increase dramatically. Monte Carlo simulations are one way of estimation the failure probabilities, however, such simulations tend to be very time-consuming. A much speedier alternative is to use models for the estimation. This paper presents a method for creating the mathematical models for the probabilities of failures of CMOS logic gates/blocks. The models of five common gates are included, i.e., NAND3, NAND4, NOR3, NOR4 and OAI22. The models can also be used to study the sensitivity of the gates' failures to their individual transistors' failures. The presented technique is applicable to larger logic cells such as 28-transistor full-adders, etc. The given models are anticipated to be useful for Pareto-optimization of logic blocks, for instance, power-and-reliability, performance-and-reliability etc.
KW - CMOS
KW - failure probability
KW - failure rate
KW - logic gate
KW - mathematical model
KW - reliability
KW - sensitivity analysis
KW - standard cell
UR - http://www.scopus.com/inward/record.url?scp=85045976947&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85045976947&partnerID=8YFLogxK
U2 - 10.1109/ICECTA.2017.8252002
DO - 10.1109/ICECTA.2017.8252002
M3 - Conference contribution
AN - SCOPUS:85045976947
T3 - 2017 International Conference on Electrical and Computing Technologies and Applications, ICECTA 2017
SP - 1
EP - 5
BT - 2017 International Conference on Electrical and Computing Technologies and Applications, ICECTA 2017
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2017 International Conference on Electrical and Computing Technologies and Applications, ICECTA 2017
Y2 - 21 November 2017 through 23 November 2017
ER -