Split-Precharge Differential Noise-Immune Threshold Logic gate (SPD-NTL)

Suryanarayana Tatapudi, Valeriu Beiu

Research output: Chapter in Book/Report/Conference proceedingChapter

15 Citations (Scopus)

Abstract

After a short review of the state-of-the-art, a new low-power differential threshold logic gate is introduced: split-precharge differential noise-immune threshold logic (SPD-NTL). It is based on combining the split-level precharge differential logic, with a technique for enhancing the noise immunity of threshold logic gates: noise suppression logic. Another idea included in the design of the SPD-NTL gates is the use of two threshold logic banks implementing f and f_bar, and working together with the noise suppression logic blocks for enhanced performances. Simulations in 0.25 μm CMOS @ 2.5 V show the functionality of the gate up to 2 GHz. An advanced layout based on high matching centroid techniques is currently under development.

Original languageEnglish
Title of host publicationLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
EditorsJose Mira, Jose R. Alvarez
PublisherSpringer Verlag
Pages49-56
Number of pages8
ISBN (Print)354040211X, 9783540402114
DOIs
Publication statusPublished - 2003
Externally publishedYes

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume2687
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

ASJC Scopus subject areas

  • Theoretical Computer Science
  • General Computer Science

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