The Performance of Parallel Prefix Adders on Nanometer FPGA

F. Kharbash, G. Chaudhry

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Carry computation is a major performance bottleneck in many high-performance digital applications. Many of the digital application use adders implicitly or explicitly in their internal architecture, and with use of Filed Programmable Gate Arrays (FPGA) as an implementation platform, the choice of an adder becomes very crucial. Thus, it is important to carefully select an adder architecture that will maximize the overall system performance at early design stage. In this paper, we investigated the implementation of five adder architectures (Ripple-Carry, Carry Look-Ahead, Brent-Kung, Kogge-Stone and Han-Carlson) on Virtex-5 FPGA that is built using the 65nm process technology. The presented results are of importance since they give an early direction for proper adder selection and integration in the design.

Original languageEnglish
Title of host publication20th International Conference on Parallel and Distributed Computing Systems, PDCS 2007
PublisherInternational Society for Computers and Their Applications (ISCA)
Pages280-284
Number of pages5
ISBN (Electronic)9781604233926
Publication statusPublished - 2007
Externally publishedYes
Event20th International Conference on Parallel and Distributed Computing Systems, PDCS 2007 - Las Vegas, United States
Duration: Sept 24 2007Sept 26 2007

Publication series

Name20th International Conference on Parallel and Distributed Computing Systems, PDCS 2007

Conference

Conference20th International Conference on Parallel and Distributed Computing Systems, PDCS 2007
Country/TerritoryUnited States
CityLas Vegas
Period9/24/079/26/07

Keywords

  • Additions
  • FPGA
  • computer arithmetic
  • parallel adders

ASJC Scopus subject areas

  • Software
  • Computer Networks and Communications
  • Hardware and Architecture

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