The quest for reliable nano computations

Valeriu Beiu

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)


    In this presentation, we explore the feasibility of designing reliable nano-architectures using practical (i.e. very small = "less than 10") redundancy factors. To this end, we begin with a thorough review of redundant design strategies for fault-tolerant nano-architectures. We then adapt three redundant design strategies -modular redundancy, von Neumann multiplexing, and reconfigurability - to majority-gate circuits, and analytically evaluate these designs' reliabilities for very small redundancy factors (including fractional factors), using arguments as needed. This analysis motivates several extensions that allow optimization of reliability for very small redundancy factors, and highlights the benefit of using majority-gates in nano-scale design, paving the way for practical fault-tolerant architectures. Besides reliability, we simultaneously address low-power designing, and show that high-performance circuits can be operated reliably at ultra low switching energies.

    Original languageEnglish
    Title of host publicationProceedings 17th 2005 International Conference on Microelectronics, ICM 2005
    Publication statusPublished - 2005
    Event17th 2005 International Conference on Microelectronics, ICM 2005 - Islamabad, Pakistan
    Duration: Dec 13 2005Dec 15 2005

    Publication series

    NameProceedings of the International Conference on Microelectronics, ICM


    Other17th 2005 International Conference on Microelectronics, ICM 2005

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering


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