TY - GEN
T1 - Thermal characterisation and liquid cooling system integration for stacked modules
AU - Tan, S. P.
AU - Toh, K. C.
AU - Chai, J. C.
AU - Pinjala, D.
AU - Khan, O. K.Navas
PY - 2007
Y1 - 2007
N2 - The demand for equipment miniaturization had resulted in high heat fluxes that need to be removed efficiently, particularly in stacked modules. Liquid cooling in microchannels is one means to meet the cooling demands, provided the high pumping power requirement can be overcome. However, when designing an integrated cooling solution for a stacked module, it may be beneficial to seek a balance between the different thermal resistances along the heat flow path than focus entirely on maximizing the heat transfer in the microchannel. A cooling solution has been developed for a two-stack electronic module with each stack dissipating 100 W. Heat flows from the chip through interconnects to the carrier and then to the liquid flowing through microchannels etched into the back of the carrier. Investigations show that determining the resistance across the chip-interconnects require careful modeling and optimization. Flip-chip and wirebond interconnects were both considered. The resistance across the interconnects can be improved by using an underfill with high conductivity compared to air. A third option involves the use of a copper slug. It can further reduce the average thermal resistance but increases the temperature non-uniformity across the package. Numerical modeling of a single-pass microchannel heatsink with channel size of 100μm by 400 μm demonstrated that a resistance of 0.179°C/W is achievable with a flowrate of 100mL/min per carrier. But it is accompanied by a high streamwise temperature rise and pressure drop. Other heatsink configurations are being considered. The current approach decouples the chip-interconnects modeling with the heatsink modeling, in order to allow similar length scales to be modeled more efficiently. However a final systems level simulation will have to be conducted to ensure the results still apply.
AB - The demand for equipment miniaturization had resulted in high heat fluxes that need to be removed efficiently, particularly in stacked modules. Liquid cooling in microchannels is one means to meet the cooling demands, provided the high pumping power requirement can be overcome. However, when designing an integrated cooling solution for a stacked module, it may be beneficial to seek a balance between the different thermal resistances along the heat flow path than focus entirely on maximizing the heat transfer in the microchannel. A cooling solution has been developed for a two-stack electronic module with each stack dissipating 100 W. Heat flows from the chip through interconnects to the carrier and then to the liquid flowing through microchannels etched into the back of the carrier. Investigations show that determining the resistance across the chip-interconnects require careful modeling and optimization. Flip-chip and wirebond interconnects were both considered. The resistance across the interconnects can be improved by using an underfill with high conductivity compared to air. A third option involves the use of a copper slug. It can further reduce the average thermal resistance but increases the temperature non-uniformity across the package. Numerical modeling of a single-pass microchannel heatsink with channel size of 100μm by 400 μm demonstrated that a resistance of 0.179°C/W is achievable with a flowrate of 100mL/min per carrier. But it is accompanied by a high streamwise temperature rise and pressure drop. Other heatsink configurations are being considered. The current approach decouples the chip-interconnects modeling with the heatsink modeling, in order to allow similar length scales to be modeled more efficiently. However a final systems level simulation will have to be conducted to ensure the results still apply.
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U2 - 10.1109/EPTC.2007.4469821
DO - 10.1109/EPTC.2007.4469821
M3 - Conference contribution
AN - SCOPUS:50049115283
SN - 1424413249
SN - 9781424413249
T3 - Proceedings of the Electronic Packaging Technology Conference, EPTC
SP - 179
EP - 183
BT - 9th Electronics Packaging Technology Conference, EPTC 2007
T2 - 9th Electronics Packaging Technology Conference, EPTC 2007
Y2 - 12 December 2007 through 12 December 2007
ER -