Threshold voltage variations make full adders reliabilities similar

Walid Ibrahim, Valeriu Beiu

    Research output: Contribution to journalArticlepeer-review

    6 Citations (Scopus)


    Addition is the most widely used arithmetic operation in digital applications. The reliability of full adder (FA) cells is crucial as they affect arithmetic logic and floating-point units, as well as cache/memory address calculations. This letter studies the reliability of five different FA designs. The analysis starts from the device level by estimating the effects threshold voltage variations will have on the reliability of scaled CMOS transistors. These estimations will then be used to calculate the reliability of the sum and carry-out signals. This letter will also briefly explore the effects of increasing the reliability of devices and of using gate-level redundancy schemes on the reliability of FAs.

    Original languageEnglish
    Article number5549917
    Pages (from-to)664-667
    Number of pages4
    JournalIEEE Transactions on Nanotechnology
    Issue number6
    Publication statusPublished - Nov 2010


    • Adders
    • Bayesian network (BN)
    • CMOS
    • reliability
    • threshold voltage
    • variations

    ASJC Scopus subject areas

    • Computer Science Applications
    • Electrical and Electronic Engineering


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