Abstract
This paper details a systematic method for significantly improving the noise margins of very fast threshold gates. The method is based on adding nonlinear terms determined from the Boolean form of the threshold function to be implemented. Simulation results support our theoretical claims. Finally, two methods for drastically reducing the dissipated power of such threshold gates down to <50%, and respectively <10% are also suggested.
| Original language | English |
|---|---|
| Pages | 1310-1313 |
| Number of pages | 4 |
| Publication status | Published - 2000 |
| Externally published | Yes |
| Event | 43rd IEEE Midwest Symposium on Circuits and Systems - Lansing, Mi, United States Duration: Aug 8 2000 → Aug 11 2000 |
Other
| Other | 43rd IEEE Midwest Symposium on Circuits and Systems |
|---|---|
| Country/Territory | United States |
| City | Lansing, Mi |
| Period | 8/8/00 → 8/11/00 |
Keywords
- CMOS integrated circuits
- Noise
- Threshold gates
- Threshold logic
- VLSI
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering