Ultra-fast noise immune CMOS threshold logic gates

Valeriu Beiu

Research output: Contribution to conferencePaperpeer-review

10 Citations (Scopus)


This paper details a systematic method for significantly improving the noise margins of very fast threshold gates. The method is based on adding nonlinear terms determined from the Boolean form of the threshold function to be implemented. Simulation results support our theoretical claims. Finally, two methods for drastically reducing the dissipated power of such threshold gates down to <50%, and respectively <10% are also suggested.

Original languageEnglish
Number of pages4
Publication statusPublished - 2000
Externally publishedYes
Event43rd IEEE Midwest Symposium on Circuits and Systems - Lansing, Mi, United States
Duration: Aug 8 2000Aug 11 2000


Other43rd IEEE Midwest Symposium on Circuits and Systems
Country/TerritoryUnited States
CityLansing, Mi


  • CMOS integrated circuits
  • Noise
  • Threshold gates
  • Threshold logic
  • VLSI

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


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