Ultra low power fault tolerant neural inspired CMOS logic

Snorre Aunet, Valeriu Beiu

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    12 Citations (Scopus)

    Abstract

    We present a new defect/fault tolerant ultra low power CMOS circuit exploiting low level redundancy. We show that wiring and transistors may be damaged while the functionality is still kept. We also demonstrate a new full adder based on the basic building block, capable of sub fJ Power-Delay-Product for supply voltages below 100 mV, in a 120 nm process. The Power-Delay-Product is reduced by about 50 % compared to the best previously published FA based on a 6 transistor reconfigurable subthreshold NOR-3, MAJ-3, NAND-3 circuit. Transistors are exploited as four terminal devices operating in subthreshold and DC characteristics for a threshold element is demonstrated by chip measurements.

    Original languageEnglish
    Title of host publicationProceedings of the International Joint Conference on Neural Networks, IJCNN 2005
    Pages2843-2848
    Number of pages6
    DOIs
    Publication statusPublished - 2005
    EventInternational Joint Conference on Neural Networks, IJCNN 2005 - Montreal, QC, Canada
    Duration: Jul 31 2005Aug 4 2005

    Publication series

    NameProceedings of the International Joint Conference on Neural Networks
    Volume5

    Other

    OtherInternational Joint Conference on Neural Networks, IJCNN 2005
    Country/TerritoryCanada
    CityMontreal, QC
    Period7/31/058/4/05

    ASJC Scopus subject areas

    • Software
    • Artificial Intelligence

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