Ultra low power fault tolerant neural inspired CMOS logic

Snorre Aunet; Valeriu Beiu

doi:10.1109/IJCNN.2005.1556376

Ultra low power fault tolerant neural inspired CMOS logic

Snorre Aunet, Valeriu Beiu

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

12 Citations (Scopus)

Abstract

We present a new defect/fault tolerant ultra low power CMOS circuit exploiting low level redundancy. We show that wiring and transistors may be damaged while the functionality is still kept. We also demonstrate a new full adder based on the basic building block, capable of sub fJ Power-Delay-Product for supply voltages below 100 mV, in a 120 nm process. The Power-Delay-Product is reduced by about 50 % compared to the best previously published FA based on a 6 transistor reconfigurable subthreshold NOR-3, MAJ-3, NAND-3 circuit. Transistors are exploited as four terminal devices operating in subthreshold and DC characteristics for a threshold element is demonstrated by chip measurements.

Original language	English
Title of host publication	Proceedings of the International Joint Conference on Neural Networks, IJCNN 2005
Pages	2843-2848
Number of pages	6
DOIs	https://doi.org/10.1109/IJCNN.2005.1556376
Publication status	Published - 2005
Event	International Joint Conference on Neural Networks, IJCNN 2005 - Montreal, QC, Canada Duration: Jul 31 2005 → Aug 4 2005

Publication series

Name	Proceedings of the International Joint Conference on Neural Networks
Volume	5

Other

Other	International Joint Conference on Neural Networks, IJCNN 2005
Country/Territory	Canada
City	Montreal, QC
Period	7/31/05 → 8/4/05

ASJC Scopus subject areas

Software
Artificial Intelligence

Access to Document

10.1109/IJCNN.2005.1556376

Cite this

Aunet, S & Beiu, V 2005, Ultra low power fault tolerant neural inspired CMOS logic. in Proceedings of the International Joint Conference on Neural Networks, IJCNN 2005., 1556376, Proceedings of the International Joint Conference on Neural Networks, vol. 5, pp. 2843-2848, International Joint Conference on Neural Networks, IJCNN 2005, Montreal, QC, Canada, 7/31/05. https://doi.org/10.1109/IJCNN.2005.1556376

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title = "Ultra low power fault tolerant neural inspired CMOS logic",

abstract = "We present a new defect/fault tolerant ultra low power CMOS circuit exploiting low level redundancy. We show that wiring and transistors may be damaged while the functionality is still kept. We also demonstrate a new full adder based on the basic building block, capable of sub fJ Power-Delay-Product for supply voltages below 100 mV, in a 120 nm process. The Power-Delay-Product is reduced by about 50 % compared to the best previously published FA based on a 6 transistor reconfigurable subthreshold NOR-3, MAJ-3, NAND-3 circuit. Transistors are exploited as four terminal devices operating in subthreshold and DC characteristics for a threshold element is demonstrated by chip measurements.",

author = "Snorre Aunet and Valeriu Beiu",

year = "2005",

doi = "10.1109/IJCNN.2005.1556376",

language = "English",

isbn = "0780390482",

series = "Proceedings of the International Joint Conference on Neural Networks",

pages = "2843--2848",

booktitle = "Proceedings of the International Joint Conference on Neural Networks, IJCNN 2005",

note = "International Joint Conference on Neural Networks, IJCNN 2005 ; Conference date: 31-07-2005 Through 04-08-2005",

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AB - We present a new defect/fault tolerant ultra low power CMOS circuit exploiting low level redundancy. We show that wiring and transistors may be damaged while the functionality is still kept. We also demonstrate a new full adder based on the basic building block, capable of sub fJ Power-Delay-Product for supply voltages below 100 mV, in a 120 nm process. The Power-Delay-Product is reduced by about 50 % compared to the best previously published FA based on a 6 transistor reconfigurable subthreshold NOR-3, MAJ-3, NAND-3 circuit. Transistors are exploited as four terminal devices operating in subthreshold and DC characteristics for a threshold element is demonstrated by chip measurements.

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T3 - Proceedings of the International Joint Conference on Neural Networks

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BT - Proceedings of the International Joint Conference on Neural Networks, IJCNN 2005

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Ultra low power fault tolerant neural inspired CMOS logic

Abstract

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