TY - GEN
T1 - Ultra low power fault tolerant neural inspired CMOS logic
AU - Aunet, Snorre
AU - Beiu, Valeriu
PY - 2005
Y1 - 2005
N2 - We present a new defect/fault tolerant ultra low power CMOS circuit exploiting low level redundancy. We show that wiring and transistors may be damaged while the functionality is still kept. We also demonstrate a new full adder based on the basic building block, capable of sub fJ Power-Delay-Product for supply voltages below 100 mV, in a 120 nm process. The Power-Delay-Product is reduced by about 50 % compared to the best previously published FA based on a 6 transistor reconfigurable subthreshold NOR-3, MAJ-3, NAND-3 circuit. Transistors are exploited as four terminal devices operating in subthreshold and DC characteristics for a threshold element is demonstrated by chip measurements.
AB - We present a new defect/fault tolerant ultra low power CMOS circuit exploiting low level redundancy. We show that wiring and transistors may be damaged while the functionality is still kept. We also demonstrate a new full adder based on the basic building block, capable of sub fJ Power-Delay-Product for supply voltages below 100 mV, in a 120 nm process. The Power-Delay-Product is reduced by about 50 % compared to the best previously published FA based on a 6 transistor reconfigurable subthreshold NOR-3, MAJ-3, NAND-3 circuit. Transistors are exploited as four terminal devices operating in subthreshold and DC characteristics for a threshold element is demonstrated by chip measurements.
UR - http://www.scopus.com/inward/record.url?scp=24944509428&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=24944509428&partnerID=8YFLogxK
U2 - 10.1109/IJCNN.2005.1556376
DO - 10.1109/IJCNN.2005.1556376
M3 - Conference contribution
AN - SCOPUS:24944509428
SN - 0780390482
SN - 9780780390485
T3 - Proceedings of the International Joint Conference on Neural Networks
SP - 2843
EP - 2848
BT - Proceedings of the International Joint Conference on Neural Networks, IJCNN 2005
T2 - International Joint Conference on Neural Networks, IJCNN 2005
Y2 - 31 July 2005 through 4 August 2005
ER -