Ultra low-power neural inspired addition: When serial might outperform parallel architectures

Valeriu Beiu, Asbjørn Djupdal, Snorre Aunet

    Research output: Contribution to journalConference articlepeer-review

    14 Citations (Scopus)


    In this paper we analyse a serial (ripple carry) and a parallel (Kogge-Stone) adder when operating in subthreshold at 100nm and 70nm. These are targeted for ultra low power consumption applications. The elementary gates used are threshold logic gates (perceptrons). Simulations have been performed both with and without considering the delay on the wires. These simulations confirm that wires play a significant role, reducing the speed advantage of the parallel adder (over the serial one) from 4.5x to 2.2-2.4x. A promising result is that the speed of both adders improves more than 10x when migrating from 100nm to 70nm. The full adder based on threshold logic gates (used in the ripple carry adder) improves on previously known full adders, achieving 1.6fJ when operated at 200mV in 120nm CMOS. Finally, the speed of the parallel adder can be matched by the serial adder when operating at only 10-20% higher V dd, while still requiring less power and energy.

    Original languageEnglish
    Pages (from-to)486-493
    Number of pages8
    JournalLecture Notes in Computer Science
    Publication statusPublished - 2005
    Event8th International Workshop on Artificial Neural Networks, IWANN 2005: Computational Intelligence and Bioinspired Systems - Vilanova i la Geltru, Spain
    Duration: Jun 8 2005Jun 10 2005

    ASJC Scopus subject areas

    • Theoretical Computer Science
    • General Computer Science


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